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'''Cortex-X5''' (Chaberton-ELP) is the successor to the '''Cortex-X4''' ({{\\|Hunter-ELP}}),<!--and '''Cortex-A720''' ({{\\|Hunter}})--> a performance-enhanced version of the <br>'''Cortex-A725''' ({{\\|Chaberton}}), low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
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<s>'''Cortex-X5''' (Chaberton-ELP)</s> is the successor to the '''Cortex-X4''' ({{\\|Hunter-ELP}}),<!--and '''Cortex-A720''' ({{\\|Hunter}})--> a performance-enhanced version of the <br>'''Cortex-A725''' ({{\\|Chaberton}}), low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
 
<!-- '''Logan''' is the successor to the {{\\|Hunter}}, low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market. ? -->
 
<!-- '''Logan''' is the successor to the {{\\|Hunter}}, low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market. ? -->
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== Cortex-X925 ==
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'''Cortex-X925''' ''(Blackhawk)'' is the successor to the '''Cortex-X4''' ({{\\|Hunter-ELP}}), a performance-enhanced version of the <br>'''Cortex-A725''' ({{\\|Chaberton}}), low-power high-performance [[ARM]] [[microarchitecture]] designed by [[Arm]] for the mobile market.
  
 
=== Cortex-X ===
 
=== Cortex-X ===
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|-
 
|-
 
|}
 
|}
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== Architecture ==
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Cortex-X925 is a high-performance CPU core designed by [[Arm]] and introduced in [[2024]].<ref>https://fuse.wikichip.org/news/7761/arm-launches-next-gen-flagship-cortex-x925/</ref> It is part of the second-generation ARMv9.2 architecture and is built on a [[3 nm]] process node. The Cortex-X925  is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing.
 +
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The Cortex-X925 is designed to be used in both homogeneous and heterogeneous {{armh|big.LITTLE|DynamIQ}} clusters, providing flexibility in various system configurations. <ref>https://developer.arm.com/documentation/102807/0001/The-Cortex-X925--core/Cortex-X925--core-features</ref>
 +
 +
=== Key features ===
 +
 +
*Support for ARMv9.2-A instruction set: the core supports A64 instruction set and AArch64 execution state at all exception levels.
 +
*10-wide decode and dispatch width: this allows the core to process more instructions per cycle, increasing overall throughput. <ref>https://www.anandtech.com/show/21399/arm-unveils-2024-cpu-core-designs-cortex-x925-a725-and-a520-arm-v9-2-redefined-for-3nm-/2</ref>
 +
*Increased L1 instruction cache (I$) bandwidth: the core features a 2x increase in L1 I$ bandwidth, ensuring quick instruction fetch and decode.
 +
*Enhanced branch prediction unit: techniques such as folded-out unconditional direct branches reduce mispredicted branches, leading
 +
:to fewer pipeline flushes and higher sustained IPC.
 +
*Doubled instruction window size: this reduces stalls and improves the efficiency of the execution pipeline.
 +
*Scalable Vector Extension (SVE) and SVE2: these extensions provide advanced SIMD and floating-point support.
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*Error protection: the core includes error protection on L1 instruction and data caches, L2 cache,
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:and MMU Translation Cache (MMU TC) with parity or ECC.
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=== Comparison ===
 +
 +
:;"Prime" core
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{| class="wikitable sortable" cellpadding="3px" style="border: 1px solid black; border-spacing: 0px; width: 100%; text-align:center;
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|-
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![[Microarchitecture|Architecture]]
 +
!{{armh|Cortex-A78|l=arch}}
 +
!{{armh|Cortex-X1|l=arch}}
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!{{armh|Cortex-X2|l=arch}}
 +
!{{armh|Cortex-X3|l=arch}}
 +
!{{armh|Cortex-X4|l=arch}}
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!{{armh|Cortex-X925|l=arch}}
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!{{armh|Cortex-X930|l=arch}}
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|-
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!Code name
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|''{{armh|Hercules|l=arch}}''
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|''Hera''
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|''{{armh|Matterhorn|l=arch}}-ELP''
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|''{{armh|Makalu|l=arch}}-ELP''
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|''{{armh|Hunter-ELP|l=arch}}''
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|''Blackhawk''
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|''Travis''
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|-
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!ISA
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| colspan="2" |[[ARMv8]].2-A
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| colspan="2" |ARMv9.0-A
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| colspan="3" |ARMv9.2-A
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|-
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!Peak clock speed
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| colspan="3" |~3.0&nbsp;GHz
 +
|~3.3&nbsp;GHz
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|~3.4&nbsp;GHz
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|~3.8&nbsp;GHz
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|~4.2&nbsp;GHz
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|-
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!Max in-flight
 +
|2x 160
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|2x 224
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|2x 288
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|2x 320
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|2x 384
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|2x 768
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|
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|-
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!L0 (Mops entries)
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|1536 <ref>{{cite book |title=Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence |url=https://www.anandtech.com/show/15813/arm-cortex-a78-cortex-x1-cpu-ip-diverging }}</ref>
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| colspan="2" |3072
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|1536
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|0
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|
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|
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|-
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!L1-I + L1-D
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|32+32 KiB
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| colspan="2" |64+64 KiB
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| colspan="2" |64+64 KiB
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|64+64 KiB
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|
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|-
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!L2
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|128–512 KiB
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| colspan="3" |0.25–1 MiB
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|0.5–2 MiB
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|2–3 MiB
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|
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|-
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!L3
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| colspan="2" |0–8 MiB <ref>{{cite book |last=Schor |first=David |date=2020-05-26 |title=Arm Cortex-X1: The First From The Cortex-X Custom Program |url=https://fuse.wikichip.org/news/3543/arm-cortex-x1-the-first-from-the-cortex-x-custom-program/ |website=WikiChip Fuse }}</ref>
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| colspan="2" |0–16 MiB
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| colspan="2" |0–32 MiB
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|
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|-
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!Decode width
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|4
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| colspan="2" |5
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|6
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|10 <ref>{{cite book |date=2023-05-29 |title=Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive |url=https://www.androidauthority.com/arm-cortex-x4-explained-3328008/ |website=Android Authority}}</ref>
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|10
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|
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|-
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!Dispatch
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|6/cycle
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| colspan="3" |8/cycle
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| colspan="2" |10/cycle
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|
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|-
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|}
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== References ==

Latest revision as of 18:31, 15 April 2025

Edit Values
Cortex-X5 (Chaberton-ELP) µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerTSMC
Introduction2024
Phase-outCancelled
Cores
Core NamesCortex-X5
Succession
Contemporary
Cortex-A725 (Chaberton)
Cortex-A730 (Gelas)

Cortex-X5 (Chaberton-ELP) is the successor to the Cortex-X4 (Hunter-ELP), a performance-enhanced version of the
Cortex-A725 (Chaberton), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X925[edit]

Cortex-X925 (Blackhawk) is the successor to the Cortex-X4 (Hunter-ELP), a performance-enhanced version of the
Cortex-A725 (Chaberton), low-power high-performance ARM microarchitecture designed by Arm for the mobile market.

Cortex-X[edit]

ARM • Cortex
Year Cortex-X Core Cortex-A Core
2020 Cortex-X1 (Hera)
Cortex-X1C (Hera-C) 		Cortex-A78 (Hercules)
Cortex-A78C (Hera Prime)
2021 Cortex-X2
(Matterhorn-ELP) 		Cortex-A710 (Matterhorn)
Cortex-A510 (Klein)
2022 Cortex-X3 (Makalu-ELP) Cortex-A715 (Makalu)
2023 Cortex-X4 (Hunter-ELP) Cortex-A720 (Hunter)
Cortex-A520 (Hayes)
2024 Cortex-X5 (Chaberton-ELP)
Cortex-X925 (Blackhawk) 		Cortex-A720AE (Hunter-AE)
Cortex-A725 (Chaberton)
2025 Cortex-X930 (Travis) Cortex-A730 (Gelas)
Cortex-A530 (Nevis)

Architecture[edit]

Cortex-X925 is a high-performance CPU core designed by Arm and introduced in 2024.[1] It is part of the second-generation ARMv9.2 architecture and is built on a 3 nm process node. The Cortex-X925 is designed to excel in single-threaded instruction per clock (IPC) performance, making it ideal for high-performance mobile computing.

The Cortex-X925 is designed to be used in both homogeneous and heterogeneous DynamIQ clusters, providing flexibility in various system configurations. [2]

Key features[edit]

  • Support for ARMv9.2-A instruction set: the core supports A64 instruction set and AArch64 execution state at all exception levels.
  • 10-wide decode and dispatch width: this allows the core to process more instructions per cycle, increasing overall throughput. [3]
  • Increased L1 instruction cache (I$) bandwidth: the core features a 2x increase in L1 I$ bandwidth, ensuring quick instruction fetch and decode.
  • Enhanced branch prediction unit: techniques such as folded-out unconditional direct branches reduce mispredicted branches, leading
to fewer pipeline flushes and higher sustained IPC.
  • Doubled instruction window size: this reduces stalls and improves the efficiency of the execution pipeline.
  • Scalable Vector Extension (SVE) and SVE2: these extensions provide advanced SIMD and floating-point support.
  • Error protection: the core includes error protection on L1 instruction and data caches, L2 cache,
and MMU Translation Cache (MMU TC) with parity or ECC.

Comparison[edit]

"Prime" core
Architecture Cortex-A78 Cortex-X1 Cortex-X2 Cortex-X3 Cortex-X4 Cortex-X925 Cortex-X930
Code name Hercules Hera Matterhorn-ELP Makalu-ELP Hunter-ELP Blackhawk Travis
ISA ARMv8.2-A ARMv9.0-A ARMv9.2-A
Peak clock speed ~3.0 GHz ~3.3 GHz ~3.4 GHz ~3.8 GHz ~4.2 GHz
Max in-flight 2x 160 2x 224 2x 288 2x 320 2x 384 2x 768
L0 (Mops entries) 1536 [4] 3072 1536 0
L1-I + L1-D 32+32 KiB 64+64 KiB 64+64 KiB 64+64 KiB
L2 128–512 KiB 0.25–1 MiB 0.5–2 MiB 2–3 MiB
L3 0–8 MiB [5] 0–16 MiB 0–32 MiB
Decode width 4 5 6 10 [6] 10
Dispatch 6/cycle 8/cycle 10/cycle

References[edit]

  1. ↑ https://fuse.wikichip.org/news/7761/arm-launches-next-gen-flagship-cortex-x925/
  2. ↑ https://developer.arm.com/documentation/102807/0001/The-Cortex-X925--core/Cortex-X925--core-features
  3. ↑ https://www.anandtech.com/show/21399/arm-unveils-2024-cpu-core-designs-cortex-x925-a725-and-a520-arm-v9-2-redefined-for-3nm-/2
  4. ↑ Arm's New Cortex-A78 and Cortex-X1 Microarchitectures: An Efficiency and Performance Divergence.
  5. ↑ Schor, David (2020-05-26). Arm Cortex-X1: The First From The Cortex-X Custom Program.
  6. ↑ (2023-05-29) Arm Cortex-X4, A720, and A520: 2024 smartphone CPUs deep dive.
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Facts about "Cortex-X5 (Chaberton-ELP) - Microarchitectures - ARM"
RDF feed
codenameCortex-X5 (Chaberton-ELP) +
designerARM Holdings +
first launched2024 +
full page namearm holdings/microarchitectures/chaberton-elp +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameCortex-X5 (Chaberton-ELP) +