Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/microarchitectures/zen 5"
(A small amount of published information has been changed.) |
(fixed) |
||
| Line 5: | Line 5: | ||
|designer=AMD | |designer=AMD | ||
|manufacturer=TSMC | |manufacturer=TSMC | ||
| − | |process=N4X | + | |introduction=2024 |
| + | |process=4 nm | ||
| + | |process 2=N4X | ||
|cores=256 | |cores=256 | ||
|cores 2=224 | |cores 2=224 | ||
| Line 20: | Line 22: | ||
|cores 13=36 | |cores 13=36 | ||
|cores 14=24 | |cores 14=24 | ||
| − | |cores | + | |cores 15=18 |
|cores 16=16 | |cores 16=16 | ||
| − | |cores | + | |cores 17=8 |
| − | |cores | + | |cores 18=6 |
|processing elements=512 | |processing elements=512 | ||
|processing elements 2=448 | |processing elements 2=448 | ||
| Line 44: | Line 46: | ||
|speculative=Yes | |speculative=Yes | ||
|renaming=Yes | |renaming=Yes | ||
| − | |isa=x86-64 | + | |isa=AMD64 |
| − | | | + | |isa 2=x86-64 |
| + | |extension=AMX <!-- (Advanced Matrix Extensions) --> | ||
| + | |extension 2=AVX | ||
| + | |extension 3=AVX2 | ||
| + | |extension 4=AVX-512 | ||
|feature=SHA | |feature=SHA | ||
| − | |feature 2=XFR 3 or 4 ( Extended frequency range) | + | |feature 2=XFR 3 or 4 <!-- (Extended frequency range) --> |
| − | |core name=Turin (EPYC server multiprocessor) | + | |core name={{amd|Turin|l=arch}} <!-- (EPYC server multiprocessor) --> |
| − | |core name 2=Da Vinci (Threadripper Workstation) | + | |core name 2={{amd|Da Vinci|l=arch}} <!-- (Threadripper Workstation) --> |
| − | |core name 3=Granite Ridge (Gaming Desktop CPU) | + | |core name 3={{amd|Granite Ridge|l=arch}} <!-- (Gaming Desktop CPU) --> |
| − | |core name 4=Strix Point (Gaming APU with RDNA3 or RDNA4) | + | |core name 4={{amd|Strix Point|l=arch}} <!-- (Gaming APU with RDNA3 or RDNA4) --> |
| + | |succession=Yes | ||
|predecessor=Zen 4 | |predecessor=Zen 4 | ||
|predecessor link=amd/microarchitectures/zen 4 | |predecessor link=amd/microarchitectures/zen 4 | ||
| − | |successor=Zen 6 or maybe a completely new microarchitecture | + | |successor=Zen 6 <!-- or maybe a completely new microarchitecture --> |
| − | | | + | |successor link=amd/microarchitectures/zen 6 |
}} | }} | ||
| − | '''Zen 5''' is a [[microarchitecture]]Already released and sold being by [[AMD]] as a successor to {{\\|Zen 4}} | + | |
| + | '''Zen 5''' is a [[microarchitecture]] Already released and sold being by [[AMD]] as a successor to {{\\|Zen 4}} | ||
== History == | == History == | ||
| − | Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 | + | Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 <ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen Processors: One Year Later]</ref> |
== Codenames == | == Codenames == | ||
| Line 66: | Line 74: | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
| − | ! Core !! C/T !! Target | + | ! Model !! Core !! C/T !! Target |
|- | |- | ||
| − | | {{amd|Turin|l=core}} || Up to ?/? || High-end server [[multiprocessors]] | + | | {{amd|EPYC 9005}} || {{amd|Turin|l=core}} || Up to ?/? || High-end EPYC server [[multiprocessors]]) |
|- | |- | ||
| − | | {{amd|Da Vinci|l=core}} || Up to ?/? || Workstation & enthusiasts market processors | + | | - || {{amd|Da Vinci|l=core}} || Up to ?/? || Threadripper Workstation & enthusiasts market processors |
|- | |- | ||
| − | | {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors | + | | {{amd|Ryzen 9000}} || {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors<br>(Gaming Desktop CPU) |
|- | |- | ||
| − | | {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU | + | | {{amd|Ryzen AI 300}} || {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU<br>(Gaming APU with RDNA3 or RDNA4) |
|} | |} | ||
| + | |||
| + | The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"), | ||
| + | :Epyc 9005 server processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors | ||
| + | :(codenamed "Strix Point"). | ||
'''Architectural Codenames:''' | '''Architectural Codenames:''' | ||
| Line 93: | Line 105: | ||
LITTLE design | LITTLE design | ||
| − | -Improved 16% IPC and clock speed | + | - Improved 16% IPC and clock speed |
- possibly more L3 cache per chiplet | - possibly more L3 cache per chiplet | ||
Latest revision as of 01:01, 17 December 2024
| Edit Values | |
| Zen 5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC |
| Introduction | 2024 |
| Process | 4 nm, N4X |
| Core Configs | 256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 16, 8, 6 |
| PE Configs | 512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | AMD64, x86-64 |
| Extensions | AMX, AVX, AVX2, AVX-512 |
| Cores | |
| Core Names | Turin, Da Vinci, Granite Ridge, Strix Point |
| Succession | |
Zen 5 is a microarchitecture Already released and sold being by AMD as a successor to Zen 4
Contents
History[edit]
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018 [1]
Codenames[edit]
Product Codenames:
| Model | Core | C/T | Target |
|---|---|---|---|
| EPYC 9005 | Turin | Up to ?/? | High-end EPYC server multiprocessors) |
| - | Da Vinci | Up to ?/? | Threadripper Workstation & enthusiasts market processors |
| Ryzen 9000 | Granite Ridge | Up to ?/? | Mainstream to high-end desktops & enthusiasts market processors (Gaming Desktop CPU) |
| Ryzen AI 300 | Strix Point | Up to ?/? | Mainstream desktop & mobile processors with GPU (Gaming APU with RDNA3 or RDNA4) |
The Zen 5 microarchitecture powers Ryzen 9000 series desktop processors (codenamed "Granite Ridge"),
- Epyc 9005 server processors (codenamed "Turin"), and Ryzen AI 300 thin and light mobile processors
- (codenamed "Strix Point").
Architectural Codenames:
| Arch | Codename |
|---|---|
| Core | Nirvana |
| CCD | Eldora |
Process Technology[edit]
Zen 5 is to be produced on a 4nm process,Zen 5c is to be produced on a 3nm process.
Architecture[edit]
LITTLE design - Improved 16% IPC and clock speed - possibly more L3 cache per chiplet
Key changes from Zen 4[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Designers[edit]
- David Suggs, chief architect
Bibliography[edit]
See Also[edit]
- AMD Zen
- Intel Meteor Lake
Facts about "Zen 5 - Microarchitectures - AMD"
| codename | Zen 5 + |
| core count | 256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 +, 28 +, 36 +, 24 +, 18 +, 16 +, 8 + and 6 + |
| designer | AMD + |
| first launched | 2024 + |
| full page name | amd/microarchitectures/zen 5 + |
| instance of | microarchitecture + |
| instruction set architecture | AMD64 + and x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Zen 5 + |
| process | 4 nm (0.004 μm, 4.0e-6 mm) + |
| processing element count | 512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 + |