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Difference between revisions of "amd/microarchitectures/zen 5"
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== History == | == History == | ||
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>. | Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018<ref>[https://www.youtube.com/watch?v=iQ_4C2TKHQ0 Ryzen™ Processors: One Year Later]</ref>. | ||
| + | |||
| + | == Codenames == | ||
| + | '''Product Codenames:''' | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Core !! C/T !! Target | ||
| + | |- | ||
| + | | {{amd|Turin|l=core}} || Up to ?/? || High-end server [[multiprocessors]] | ||
| + | |- | ||
| + | | {{amd|Da Vinci|l=core}} || Up to ?/? || Workstation & enthusiasts market processors | ||
| + | |- | ||
| + | | {{amd|Granite Ridge|l=core}} || Up to ?/? || Mainstream to high-end desktops & enthusiasts market processors | ||
| + | |- | ||
| + | | {{amd|Strix Point|l=core}} || Up to ?/? || Mainstream desktop & mobile processors with GPU | ||
| + | |} | ||
| + | |||
| + | '''Architectural Codenames:''' | ||
| + | {| class="wikitable" | ||
| + | |- | ||
| + | ! Arch !! Codename | ||
| + | |- | ||
| + | | Core || Nirvana | ||
| + | |- | ||
| + | | CCD || Eldora | ||
| + | |} | ||
== Process Technology == | == Process Technology == | ||
Zen 5 is speculated to be produced on a [[3nm process]]. | Zen 5 is speculated to be produced on a [[3nm process]]. | ||
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== Architecture == | == Architecture == | ||
Revision as of 21:33, 9 October 2022
| Edit Values | |
| Zen 5 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | TSMC or Samsung |
| Process | 3 nm |
| Core Configs | 256, 224, 192, 144, 128, 96, 72, 64, 56, 48, 32, 28, 36, 24, 18, 12 |
| PE Configs | 512, 448, 384, 288, 256, 192, 144, 128, 112, 96, 64, 56, 60, 40, 30, 20 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64, AVX512, AMX (Advanced Matrix Extensions) |
| Cores | |
| Core Names | Turin (EPYC server multiprocessor), Da Vinci (Threadripper Workstation), Granite Ridge (Gaming Desktop CPU), Strix Point (Gaming APU with RDNA3 or RDNA4) |
| Succession | |
Zen 5 is a planned microarchitecture being developed by AMD as a successor to Zen 4.
Contents
History
Zen 5 was first mentioned by lead architect Michael Clark during a discussion on April 9th, 2018[1].
Codenames
Product Codenames:
| Core | C/T | Target |
|---|---|---|
| Turin | Up to ?/? | High-end server multiprocessors |
| Da Vinci | Up to ?/? | Workstation & enthusiasts market processors |
| Granite Ridge | Up to ?/? | Mainstream to high-end desktops & enthusiasts market processors |
| Strix Point | Up to ?/? | Mainstream desktop & mobile processors with GPU |
Architectural Codenames:
| Arch | Codename |
|---|---|
| Core | Nirvana |
| CCD | Eldora |
Process Technology
Zen 5 is speculated to be produced on a 3nm process.
Architecture
Little is currently known about the architectural improvements that are being done to Zen 5.
-big.LITTLE design -More IPC and clock speed - possibly more L3 cache per chiplet
Key changes from Zen 4
 |
This section is empty; you can help add the missing info by editing this page. |
Designers
- David Suggs, chief architect
Bibliography
See Also
- AMD Zen
- Intel Meteor Lake
Facts about "Zen 5 - Microarchitectures - AMD"
| codename | Zen 5 + |
| core count | 256 +, 224 +, 192 +, 144 +, 128 +, 96 +, 72 +, 64 +, 56 +, 48 +, 32 +, 28 +, 36 +, 24 +, 18 + and 12 + |
| designer | AMD + |
| full page name | amd/microarchitectures/zen 5 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + and AVX512, AMX (Advanced Matrix Extensions) + |
| manufacturer | TSMC or Samsung + |
| microarchitecture type | CPU + |
| name | Zen 5 + |
| process | 3 nm (0.003 μm, 3.0e-6 mm) + |
| processing element count | 512 +, 448 +, 384 +, 288 +, 256 +, 192 +, 144 +, 128 +, 112 +, 96 +, 64 +, 56 +, 60 +, 40 +, 30 + and 20 + |