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Difference between revisions of "amd/microarchitectures/k8"
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|l1i=64 KiB | |l1i=64 KiB | ||
|l1i per=core | |l1i per=core | ||
Revision as of 23:49, 18 June 2023
| Edit Values | |
| K8 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Introduction | September 23, 2003 |
| Process | 130 nm, 90 nm, 65 nm |
| Core Configs | 1, 2 |
| Pipeline | |
| OoOE | Yes |
| Reg Renaming | Yes |
| Decode | 3 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MMX, SSE, SSE2, SSE3 (some steppings), 3DNow! extension 6=RISC-V |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| Succession | |
K8 (Hammer) was the microarchitecture developed by AMD as a successor to K7. K8 was superseded by K10 in 2007.
Contents
Architecture
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This section is empty; you can help add the missing info by editing this page. |
Die Shot
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This section is empty; you can help add the missing info by editing this page. |
All K8 Chips
| K8 Chips | ||||||
|---|---|---|---|---|---|---|
| Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
| Count: 0 | ||||||
See also
Facts about "K8 - Microarchitectures - AMD"
| codename | K8 + |
| core count | 1 + and 2 + |
| designer | AMD + |
| first launched | September 23, 2003 + |
| full page name | amd/microarchitectures/k8 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K8 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) +, 90 nm (0.09 μm, 9.0e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |