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! Cores !! {{intel|Hyper-Threading|HT}} !! {{x86|AVX}} !! {{x86|AVX2}} !! {{x86|AVX512}} !! {{intel|Thermal Velocity Boost|TVB}} !! [[ECC]]
 
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| [[File:core i5 logo (2020).png|50px|link=intel/core_i5]] || {{intel|Core i5}} || Mid-range Performance || [[hexa-core|Hexa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
 
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| [[File:core i7 logo (2015).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
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| [[File:core i7 logo (2020).png|50px|link=intel/core_i7]] || {{intel|Core i7}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|no}}
 
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| [[File:core i9 logo (2015).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
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| [[File:core i9 logo (2020).png|50px|link=intel/core_i9]] || {{intel|Core i9}} || High-end Performance || [[octa-core|Octa]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}}
 
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| [[File:xeon logo (2021).png|50px|link=intel/xeon]] || {{intel|Xeon}} || 1S Server & Workstation || [[4-8]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
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| [[File:xeon logo (2021).png|50px|link=intel/xeon]] || {{intel|Xeon}} || 1S Server & Workstation || [[quad-core|4]]-[[octa-core|8]] || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|yes}} || {{tchk|no}} || {{tchk|yes}}
 
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Latest revision as of 11:55, 20 November 2021

Edit Values
Rocket Lake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
IntroductionMarch 16, 2021
Process14 nm
Core Configs4, 6, 8
Pipeline
TypeSuperscalar, Superpipeline
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Decode5-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX512F, SHA
Cache
L1I Cache48 KiB/core
12-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache512 KiB/core
8-way set associative
L3 Cache2 MiB/core
16-way set associative
Cores
Core NamesCypress Cove
Succession
Contemporary
Tiger Lake

Rocket Lake (RKL) is a microarchitecture designed by Intel as a successor to Comet Lake for desktops and single-socket servers.


Codenames[edit]

Core Description Graphics Target
Rocket Lake S Mainstream performance GT2 Desktop performance to value, AiOs, and minis
Rocket Lake U Ultra-low power GT2 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room

Brands[edit]

Intel has released Rocket Lake under the following brand families:

Logo Family General Description Differentiating Features
Cores HT AVX AVX2 AVX512 TVB ECC
core i5 logo (2020).png Core i5 Mid-range Performance Hexa ✔ ✔ ✔ ✔ ✘ ✘
core i7 logo (2020).png Core i7 High-end Performance Octa ✔ ✔ ✔ ✔ ✘ ✘
core i9 logo (2020).png Core i9 High-end Performance Octa ✔ ✔ ✔ ✔ ✔ ✘
50px Xeon 1S Server & Workstation 4-8 ✔ ✔ ✔ ✔ ✘ ✔

Release Dates[edit]

Rocket Lake was officially introduced on March 16, 2021 and went on sale from March 30, 2021. Limited quantities of the Core i7-11700K were (accidentally?) available through the German reseller Mindfactory on March 6, 2021.

The Xeon W-1300 Line using Rocket Lake is expected to be officially launched in Q3/2021.

Compatibility[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Rocket Lake will feature the same LGA1200 socket as Comet Lake. Rocket Lake is backwards compatible with Comet Lake. Rocket Lake will have new motherboards and a new 500 series chipset. Rocket Lake will not be compatible with Alder Lake.

Compiler support[edit]

Compiler Arch-Specific Arch-Favorable
ICC -march=? -mtune=?
GCC -march=rocketlake -mtune=rocketlake
LLVM -march=? -mtune=?
Visual Studio /arch:AVX512 /?

CPUID[edit]

Further information: Intel CPUIDs
Core Extended
Family 		Family Extended
Model 		Model Stepping
S 0 0x6 0xA 0x7 0x0-0x1
Family 6 Model 167 Stepping 0-1
Stepping: A0=0, B0=1

Architecture[edit]

Key changes from Comet Lake[edit]

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
  • Display
  • I/O
    • PCIe 4.0 (from 3.0)
  • Memory
    • Faster memory for mainstream desktops (i.e., Rocket Lake S) DDR4-3200 (from DDR4-2933)
  • Packaging

See also[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/rocket_lake&oldid=99581"
Facts about "Rocket Lake - Microarchitectures - Intel"
RDF feed
codenameRocket Lake +
core count4 +, 6 + and 8 +
designerIntel +
first launchedMarch 16, 2021 +
full page nameintel/microarchitectures/rocket lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameRocket Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process14 nm (0.014 μm, 1.4e-5 mm) +