Difference between revisions of "samsung/microarchitectures/m5"

	Edit Values
	Exynos M5 (Lion) µarch
	General Info
Arch Type	CPU
Designer	Samsung
Manufacturer	Samsung
Introduction	2020
Process	7 nm
Core Configs	2
	Pipeline
Type	Superscalar, Superpipeline
OoOE	Yes
Speculative	Yes
Reg Renaming	Yes
Stages	16
Decode	6-way
	Instructions
ISA	ARMv8.2
	Cache
L1I Cache	64 KiB/core; 4-way set associative
L1D Cache	64 KiB/core; 8-way set associative
L2 Cache	512 KiB/core; 8-way set associative
L3 Cache	2 MiB/cluster; 16-way set associative
	Succession
	M4 (Cheetah)

Latest revision as of 12:56, 22 January 2026

Exynos M5 (Lion) <aka Mongoose 5 > is the successor to the Exynos M4 (Cheetah) <aka Mongoose 4 >, a 7 nm ARM microarchitecture designed by Samsung for their consumer electronics.

Process Technology[edit]

The M5 is fabricated on Samsung's 7 nm process (7LPP).

Compiler support[edit]

Compiler	Arch-Specific	Arch-Favorable
GCC	`-mcpu=exynos-m5`	`-mtune=exynos-m5`
LLVM	`-mcpu=exynos-m5`	`-mtune=exynos-m5`

Architecture[edit]

Key changes from M4 (Cheetah)[edit]

Front end
- Larger instruction queue (60 entries, up from 48)
- Improved mispredict penalty (15 cycles, down from 16)
Back end
- LSU execution units reorganized
  - Two new 32b integer ALU pipes
- Floating-point execution units reorganized
  - Three new dedicted NEON dot product EUs

This list is incomplete; you can help by expanding it.

Block Diagram[edit]

Individual Core[edit]

Memory Hierarchy[edit]

Cache
- L1I Caches
  - 64 KiB, 4-way set associative
    - 128 B line size, per core
  - Parity-protected
- L1D Cache
  - 64 KiB, 8-way set associative
    - 64 B line size, per core
  - 4 cycles for fastest load-to-use
  - 32 B/cycle load bandwidth
  - 16 B/cycle store bandwidth
- L2 Cache
  - 512 KiB, 8-way set associative
  - Inclusive of L1
  - 12 cycles latency
  - 32 B/cycle bandwidth
- L3 Cache
  - 2 MiB, 16-way set associative
    - 1 MiB slice/core
  - Exlusive of L2
  - ~37-cycle typical (NUCA)
- BIU
  - 80 outstanding transactions

The M3 TLB consists of dedicated L1 TLB for instruction
cache (ITLB) and another one for data cache (DTLB).
Additionally, there is a unified L2 TLB (STLB).

TLBs
- ITLB
  - 512-entry
- DTLB
  - 32-entry
  - 512-entry Mid-level DTLB
- STLB
  - 4,096-entry, per core

BPU
- 4K-entry main BTB
- 128-entry µBTB
- 64-entry return stack
- 16K-entry L2 BTB

All M5 Processors[edit]

	List of M5-based Processors
	Main processor					Integrated Graphics
Model	Family	Launched	Arch	Cores	Frequency	GPU	Frequency
990	Exynos	2020	Mongoose 5, Cortex-A76, Cortex-A55	8	2.6 GHz 2,600 MHz 2,600,000 kHz , 3 GHz 3,000 MHz 3,000,000 kHz , 2.1 GHz 2,100 MHz 2,100,000 kHz	Mali-G77	832 MHz 0.832 GHz 832,000 KHz
Count: 1

Bibliography[edit]

LLVM: lib/Target/AArch64/AArch64SchedExynosM5.td

@@ Line 2: / Line 2: @@
 {{microarchitecture
 |atype=CPU
-|name= Lion M5
+|name=Exynos M5 (Lion)
 |designer=Samsung
 |manufacturer=Samsung
@@ Line 28: / Line 28: @@
 |l3 per=cluster
 |l3 desc=16-way set associative
-|predecessor=M4
+|predecessor=M4 (Cheetah)
 |predecessor link=samsung/microarchitectures/m4
 }}
-'''Exynos M5''' ('''Lion''') is the successor to the {{\\|Mongoose 4}}, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
+'''Exynos M5''' ('''Lion''') <aka ''{{\\|Mongoose 5}}'' > is the successor to the [[Exynos]] {{\\|M4}} (Cheetah) <aka ''{{\\|Mongoose 4}}'' >, a [[7 nm]] [[ARM]] microarchitecture designed by [[Samsung]] for their consumer electronics.
 == Process Technology ==
@@ Line 48: / Line 48: @@
 == Architecture ==
-=== Key changes from {{\\|M4}} ===
+=== Key changes from {{\\|M4}} (Cheetah) ===
 * Front end
 ** Larger [[instruction queue]] (60 entries, up from 48)
@@ Line 65: / Line 65: @@
 === Memory Hierarchy ===
+{| border="0" cellpadding="5" width="100%"
+|-
+|width="50%" valign="top" align="left"|
 * Cache
 ** L1I Caches
 *** 64 KiB, 4-way set associative
-**** 128 B line size
+**** 128 B line size, per core
-**** per core
 *** Parity-protected
 ** L1D Cache
 *** 64 KiB, 8-way set associative
-**** 64 B line size
+**** 64 B line size, per core
-**** per core
 *** 4 cycles for fastest load-to-use
 *** 32 B/cycle load bandwidth
@@ Line 90: / Line 91: @@
 ** BIU
 *** 80 outstanding transactions
+|width="50%" valign="top" align="left"|
-The M3 TLB consists of dedicated L1 TLB for instruction cache (ITLB) and another one for data cache (DTLB). Additionally, there is a unified L2 TLB (STLB).
+The M3 TLB consists of dedicated L1 TLB for instruction <br>cache (ITLB) and another one for data cache (DTLB). <br>Additionally, there is a unified L2 TLB (STLB).
 * TLBs
@@ Line 100: / Line 101: @@
 *** 512-entry Mid-level DTLB
 ** STLB
-*** 4,096-entry
+*** 4,096-entry, per core
-*** Per core
 * BPU
@@ Line 108: / Line 108: @@
 ** 64-entry return stack
 ** 16K-entry L2 BTB
+|}
+== All M5 Processors ==
+<!-- NOTE:
+           This table is generated automatically from the data in the actual articles.
+           If a microprocessor is missing from the list, an appropriate article for it needs to be
+           created and tagged accordingly.
+           Missing a chip? please dump its name here: https://en.wikichip.org/wiki/WikiChip:wanted_chips
+-->
+{{comp table start}}
+<table class="comptable sortable tc5 tc6 tc7">
+{{comp table header|main|7:List of M5-based Processors}}
+{{comp table header|main|5:Main processor|2:Integrated Graphics}}
+{{comp table header|cols|Family|Launched|Arch|Cores|%Frequency|GPU|%Frequency}}
+{{#ask: [[Category:microprocessor models by samsung]] [[microarchitecture::~*M5*||Mongoose 5||Exynos 5]]
+ |?full page name
+ |?model number
+ |?family
+ |?first launched
+ |?microarchitecture
+ |?core count
+ |?base frequency#GHz
+ |?integrated gpu
+ |?integrated gpu base frequency
+ |format=template
+ |template=proc table 3
+ |userparam=9
+ |mainlabel=-
+ |valuesep=,
+}}
+{{comp table count|ask=[[Category:microprocessor models by samsung]] [[microarchitecture::~*M5*||Mongoose 5||Exynos 5]]}}
+</table>
+{{comp table end}}
 == Bibliography ==
 * LLVM: lib/Target/AArch64/AArch64SchedExynosM5.td

codename	Exynos M5 (Lion) +
core count	2 +
designer	Samsung +
first launched	2020 +
full page name	samsung/microarchitectures/m5 +
instance of	microarchitecture +
instruction set architecture	ARMv8.2 +
manufacturer	Samsung +
microarchitecture type	CPU +
name	Exynos M5 (Lion) +
pipeline stages	16 +
process	7 nm (0.007 μm, 7.0e-6 mm) +

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