Semiconductor & Computer Engineering
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Difference between revisions of "centaur/microarchitectures/cha"
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=== NCORE === | === NCORE === | ||
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<div style="float: left;">[[File:cha soc ncore.png|300px]]</div> | <div style="float: left;">[[File:cha soc ncore.png|300px]]</div> | ||
<div style="float: left;">[[File:cha soc ncore (2).png|300px]]</div> | <div style="float: left;">[[File:cha soc ncore (2).png|300px]]</div> | ||
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== Bibliography == | == Bibliography == | ||
Revision as of 17:48, 22 January 2020
| Edit Values | |
| CHA µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Centaur Technology |
| Manufacturer | TSMC |
| Process | 16 nm |
| Core Configs | 8 |
| Instructions | |
| ISA | x86-64 |
CHA is a 16-nanometer x86 SoC microarchitecture designed by Centaur Technology for the server market.
Contents
Process technology
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This section is empty; you can help add the missing info by editing this page. |
Architecture
Key changes from CN
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This section is empty; you can help add the missing info by editing this page. |
Block Diagram
CHA SoC
CNS Core
NCORE NPU
Overview
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This section is empty; you can help add the missing info by editing this page. |
CNS Core
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This section is empty; you can help add the missing info by editing this page. |
NCORE NPU
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This section is empty; you can help add the missing info by editing this page. |
Die
SoC
- TSMC 16 nm process
- 195 mm²
Core group
NCORE
.png)
Bibliography
- Centaur. personal communication. November 2019.
See also
- Direct Competition
Facts about "CHA - Microarchitectures - Centaur Technology"
| codename | CHA + |
| core count | 8 + |
| designer | Centaur Technology + |
| full page name | centaur/microarchitectures/cha + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | CHA + |
| process | 16 nm (0.016 μm, 1.6e-5 mm) + |