From WikiChip
Difference between revisions of "centaur/microarchitectures/cha"
< centaur

(cha)
 
Line 10: Line 10:
 
}}
 
}}
 
'''CHA''' is a [[16-nanometer]] [[x86]] SoC microarchitecture designed by [[Centaur Technology]] for the server market.
 
'''CHA''' is a [[16-nanometer]] [[x86]] SoC microarchitecture designed by [[Centaur Technology]] for the server market.
 +
 +
== Process technology ==
 +
{{empty section}}
 +
 +
== Architecture ==
 +
=== Key changes from {{\\|CN}} ===
 +
{{empty section}}
 +
 +
== Overview ==
 +
{{empty section}}
 +
 +
== CNS Core ==
 +
{{empty section}}
 +
 +
== NCORE NPU ==
 +
{{empty section}}
 +
 +
== Die ==
 +
{{empty section}}
 +
 +
== Bibliography ==
 +
* {{bib|personal|November 2019|Centaur}}
 +
 +
== See also ==
 +
* Direct Competition
 +
** {{amd|Zen 2|l=arch}}
 +
** {{intel|Ice Lake (Server)|l=arch}}

Revision as of 16:39, 22 January 2020

Edit Values
CHA µarch
General Info
Arch TypeCPU
DesignerCentaur Technology
ManufacturerTSMC
Process16 nm
Core Configs8
Instructions
ISAx86-64

CHA is a 16-nanometer x86 SoC microarchitecture designed by Centaur Technology for the server market.

Process technology

New text document.svg This section is empty; you can help add the missing info by editing this page.

Architecture

Key changes from CN

New text document.svg This section is empty; you can help add the missing info by editing this page.

Overview

New text document.svg This section is empty; you can help add the missing info by editing this page.

CNS Core

New text document.svg This section is empty; you can help add the missing info by editing this page.

NCORE NPU

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography

  • Centaur. personal communication. November 2019.

See also

codenameCHA +
core count8 +
designerCentaur Technology +
full page namecentaur/microarchitectures/cha +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerTSMC +
microarchitecture typeCPU +
nameCHA +
process16 nm (0.016 μm, 1.6e-5 mm) +