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'''Snapdragon 865''' is a high-performance {{arch|64}} [[ARM]] [[system on a chip]] designed by [[Qualcomm]] and introduced in late [[2019]]. Fabricated on TSMC's [[7nm process]] ([[N7P]]), the 865 features four [[Kryo 585 Silver]] high-efficiency cores operating at 1.8 GHz along with three high-performance [[Kryo 585 Gold]] operating at 2.42 GHz and another prime [[Kryo 585 Gold]] core operating at 2.84 GHz. The Snapdragon 865 integrates the {{qualcomm|Adreno 650}} [[GPU]] operation at 600 MHz and supports up to 16 GiB of quad-channel LPDDR5-5500 memory.
 
'''Snapdragon 865''' is a high-performance {{arch|64}} [[ARM]] [[system on a chip]] designed by [[Qualcomm]] and introduced in late [[2019]]. Fabricated on TSMC's [[7nm process]] ([[N7P]]), the 865 features four [[Kryo 585 Silver]] high-efficiency cores operating at 1.8 GHz along with three high-performance [[Kryo 585 Gold]] operating at 2.42 GHz and another prime [[Kryo 585 Gold]] core operating at 2.84 GHz. The Snapdragon 865 integrates the {{qualcomm|Adreno 650}} [[GPU]] operation at 600 MHz and supports up to 16 GiB of quad-channel LPDDR5-5500 memory.
  
−
This SoC is designed to be paired with the Snapdragon X55 5G Modem in order to provide 5G connectivity.
+
The Snapdragon 865 is designed to be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.
 +
 
 +
== Cache ==
 +
{{main|arm_holdings/microarchitectures/cortex-a77#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Cortex-A77 § Cache|l2=Cortex-A55 § Cache}}
 +
 
 +
Prime {{armh|Cortex-A77|l=arch}}:
 +
{{cache size
 +
|l1 cache=128 KiB
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=1x512 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
3 core cluster {{armh|Cortex-A77|l=arch}}:
 +
{{cache size
 +
|l1 cache=384 KiB
 +
|l1i cache=192 KiB
 +
|l1i break=3x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=192 KiB
 +
|l1d break=3x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=768 KiB
 +
|l2 break=3x256 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
Quad-core cluster {{armh|Cortex-A55|l=arch}}:
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=4x128 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 
 +
* 4 MiB L3
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR5-5500
 +
|type=LPDDR4X-4266
 +
|ecc=No
 +
|max mem=16 GiB
 +
|controllers=1
 +
|channels=4
 +
|width=16 bit
 +
|max bandwidth=40.98 GiB/s
 +
|frequency=2750 MHz
 +
|bandwidth schan=10.24 GiB/s
 +
|bandwidth dchan=20.49 GiB/s
 +
|bandwidth qchan=40.98 GiB/s
 +
}}
 +
 
 +
== DSP ==
 +
{{#set: dsp|Hexagon 698 DSP}}
 +
This chip features [[Qualcomm]]'s {{qualcomm|Hexagon}} {{qualcomm|Hexagon 698|698}} DSP.
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Adreno 650 GPU
 +
| designer            = Qualcomm
 +
| execution units    =
 +
| max displays        = 2
 +
| max memory          =
 +
| frequency          = 250 MHz
 +
| max frequency      = 600 MHz
 +
 
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          =
 +
| output edp          =
 +
| output dp          =
 +
| output hdmi        =
 +
| output vga          =
 +
| output dvi          =
 +
 
 +
| directx ver        = 12
 +
| opengl ver        =
 +
| opengl es ver      = 3.2
 +
| opencl ver        = 2.0
 +
| vulkan ver        = 1.1
 +
| hdmi ver          =
 +
| dp ver            =
 +
| edp ver            =
 +
| max res hdmi      =
 +
| max res hdmi freq  =
 +
| max res dp        =
 +
| max res dp freq    =
 +
| max res edp        =
 +
| max res edp freq  =
 +
| max res vga        =
 +
| max res vga freq  =
 +
}}
 +
 
 +
* Codec: H.265 (HEVC), H.264 (AVC), HDR10, HDR10+, HLG, VP8, VP9
 +
* HDR Playback Codec support for HDR10+, HDR10, HLG and Dolby Vision
 +
* Volumetric VR video playback
 +
* 8K 360 VR video playback
 +
 
 +
== Camera ==
 +
* ISP
 +
** Qualcomm Spectra 480 image signal processor
 +
*** Dual 14-bit CV-ISPs
 +
*** Hardware accelerator for computer vision (CV-ISP)
 +
** ZSL
 +
*** Up to 30 MP dual camera
 +
*** Up to 64 MP single camera
 +
** 200 MP Single
 +
 
 +
* Photo Capture: HEIF photo capture
 +
* Video Capture:
 +
** Dolby Vision, HDR10, HDR10+, HEVC
 +
** 4K video capture with simultaneous 64 MP photo capture
 +
** Rec. 2020 color gamut video capture
 +
** Up to 10-bit color depth video capture
 +
** Slow motion video capture up to 720p at 960fps, HEVC Video Capture
 +
 
 +
== Connectivity ==
 +
* From the FastConnect 6800 Module
 +
** Wi-Fi
 +
*** Standards: 802.11ax, 802.11ac wave 2, 802.11a/b/g, 802.11n
 +
*** Bands: 2.4 GHz, 5 GHz
 +
*** Peak Speed: 1.774 Gbps
 +
*** 1024 QAM, 8x8 Sounding, MU-MIMO, Dual-band simultaneous (DBS), OFDMA, Target Wake-up Time (TWT)
 +
** Bluetooth
 +
*** Bluetooth 5.1
 +
 
 +
== Location ==
 +
* Systems: GPS, GLONASS, Beidou, Galileo, QZSS, SBAS, Dual frequency GNSS
 +
 
 +
== Utilizing devices ==
 +
<!--
 +
* [[used by::PHONE_HERE]]
 +
-->
 +
{{expand list}}
 +
 
 +
== Documents ==
 +
* [[:File:File:qualcomm-snapdragon-865-5g-mobile-platform-product-brief.pdf]]
 +
|Product Brief]]

Revision as of 16:48, 29 December 2019

Edit Values
Snapdragon 865
sd865 (front).png
General Info
DesignerQualcomm,
ARM Holdings
ManufacturerTSMC
Model NumberSDM865
Part NumberSM8250
MarketMobile
IntroductionDecember 4, 2019 (announced)
March, 2020 (launched)
General Specs
FamilySnapdragon 800
Series800
Frequency1,800 MHz, 2,420 MHz, 2,840 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A77, Cortex-A55
Core NameKryo 585 Gold, Kryo 585 Silver
Process7 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads8
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
sd865 (back).png
Succession
Block Diagram
Front
Back

Snapdragon 865 is a high-performance 64-bit ARM system on a chip designed by Qualcomm and introduced in late 2019. Fabricated on TSMC's 7nm process (N7P), the 865 features four Kryo 585 Silver high-efficiency cores operating at 1.8 GHz along with three high-performance Kryo 585 Gold operating at 2.42 GHz and another prime Kryo 585 Gold core operating at 2.84 GHz. The Snapdragon 865 integrates the Adreno 650 GPU operation at 600 MHz and supports up to 16 GiB of quad-channel LPDDR5-5500 memory.

The Snapdragon 865 is designed to be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.

Cache

Main articles: Cortex-A77 § Cache and Cortex-A55 § Cache


Prime Cortex-A77:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  1x512 KiB8-way set associative 

3 core cluster Cortex-A77:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$384 KiB
393,216 B
0.375 MiB
L1I$192 KiB
196,608 B
0.188 MiB
3x64 KiB4-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
3x64 KiB4-way set associative 
L2$768 KiB
0.75 MiB
786,432 B
7.324219e-4 GiB
  3x256 KiB8-way set associative 

Quad-core cluster Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB8-way set associative 
  • 4 MiB L3

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem16 GiB
Frequency2750 MHz
Controllers1
Channels4
Width16 bit
Max Bandwidth40.98 GiB/s
41,963.52 MiB/s
44.002 GB/s
44,001.94 MB/s
0.04 TiB/s
0.044 TB/s
Bandwidth
Single 10.24 GiB/s
Double 20.49 GiB/s
Quad 40.98 GiB/s

DSP

This chip features Qualcomm's Hexagon 698 DSP.

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUAdreno 650 GPU
DesignerQualcomm
Max Displays2
Frequency250 MHz
0.25 GHz
250,000 KHz
Burst Frequency600 MHz
0.6 GHz
600,000 KHz
Standards
DirectX12
OpenCL2.0
OpenGL ES3.2
Vulkan1.1
  • Codec: H.265 (HEVC), H.264 (AVC), HDR10, HDR10+, HLG, VP8, VP9
  • HDR Playback Codec support for HDR10+, HDR10, HLG and Dolby Vision
  • Volumetric VR video playback
  • 8K 360 VR video playback

Camera

  • ISP
    • Qualcomm Spectra 480 image signal processor
      • Dual 14-bit CV-ISPs
      • Hardware accelerator for computer vision (CV-ISP)
    • ZSL
      • Up to 30 MP dual camera
      • Up to 64 MP single camera
    • 200 MP Single
  • Photo Capture: HEIF photo capture
  • Video Capture:
    • Dolby Vision, HDR10, HDR10+, HEVC
    • 4K video capture with simultaneous 64 MP photo capture
    • Rec. 2020 color gamut video capture
    • Up to 10-bit color depth video capture
    • Slow motion video capture up to 720p at 960fps, HEVC Video Capture

Connectivity

  • From the FastConnect 6800 Module
    • Wi-Fi
      • Standards: 802.11ax, 802.11ac wave 2, 802.11a/b/g, 802.11n
      • Bands: 2.4 GHz, 5 GHz
      • Peak Speed: 1.774 Gbps
      • 1024 QAM, 8x8 Sounding, MU-MIMO, Dual-band simultaneous (DBS), OFDMA, Target Wake-up Time (TWT)
    • Bluetooth
      • Bluetooth 5.1

Location

  • Systems: GPS, GLONASS, Beidou, Galileo, QZSS, SBAS, Dual frequency GNSS

Utilizing devices

This list is incomplete; you can help by expanding it.

Documents

|Product Brief]]

Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/snapdragon_800/865&oldid=95236"
Facts about "Snapdragon 865 - Qualcomm"
RDF feed
back imageFile:sd865 (back).png +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,420 MHz (2.42 GHz, 2,420,000 kHz) + and 2,840 MHz (2.84 GHz, 2,840,000 kHz) +
core count8 +
core nameKryo 585 Gold + and Kryo 585 Silver +
designerQualcomm + and ARM Holdings +
dspHexagon 698 DSP +
familySnapdragon 800 +
first announcedDecember 4, 2019 +
first launchedMarch 2020 +
full page namequalcomm/snapdragon 800/865 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuAdreno 650 GPU +
integrated gpu base frequency250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu designerQualcomm +
integrated gpu max frequency600 MHz (0.6 GHz, 600,000 KHz) +
isaARMv8 +
isa familyARM +
l1$ size128 KiB (131,072 B, 0.125 MiB) +, 384 KiB (393,216 B, 0.375 MiB) + and 512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +, 192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +, 192 KiB (196,608 B, 0.188 MiB) + and 256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) + and 0.75 MiB (768 KiB, 786,432 B, 7.324219e-4 GiB) +
ldateMarch 2020 +
main imageFile:sd865 (front).png +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth40.98 GiB/s (41,963.52 MiB/s, 44.002 GB/s, 44,001.94 MB/s, 0.04 TiB/s, 0.044 TB/s) +
max memory channels4 +
microarchitectureCortex-A77 + and Cortex-A55 +
model numberSDM865 +
nameSnapdragon 865 +
part numberSM8250 +
process7 nm (0.007 μm, 7.0e-6 mm) +
series800 +
smp max ways1 +
supported memory typeLPDDR4X-4266 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +