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'''EPYC 7252P''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252P has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 
'''EPYC 7252P''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7252P has a TDP of 120 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
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== Cache ==
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{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
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{{cache size
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|l1 cache=512 KiB
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|l1i cache=256 KiB
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|l1i break=8x32 KiB
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|l1i desc=8-way set associative
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|l1d cache=256 KiB
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|l1d break=8x32 KiB
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|l1d desc=8-way set associative
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|l2 cache=4 MiB
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|l2 break=8x512 KiB
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|l2 desc=8-way set associative
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|l2 policy=write-back
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|l3 cache=64 MiB
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|l3 break=4x16 MiB
 +
}}

Revision as of 15:24, 6 August 2019

Edit Values
EPYC 7252P
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7252P
Part Number100-000000081
MarketServer
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
ShopAmazon
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency2,800 MHz
Turbo Frequency3,200 MHz
Clock multiplier28
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (3 dies)
Word Size64 bit
Cores8
Threads16
Max Memory4 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP120 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094

EPYC 7252P is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7252P has a TDP of 120 W with a base frequency of 2.8 GHz and a boost frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back
L3$64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
  4x16 MiB  
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