From WikiChip
Difference between revisions of "qualcomm/snapdragon 800/855"
< qualcomm

Line 40: Line 40:
  
 
The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.
 
The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.
 +
 +
== Cache ==
 +
{{main|arm_holdings/microarchitectures/cortex-a76#Memory_Hierarchy|arm_holdings/microarchitectures/cortex-a55#Memory_Hierarchy|l1=Cortex-A76 § Cache|l2=Cortex-A55 § Cache}}
 +
 +
1+3 core cluster {{armh|Cortex-A76|l=arch}}:
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=1 MiB
 +
|l2 break=4x256 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
Quad-core cluster {{armh|Cortex-A55|l=arch}}:
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=4x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=4x64 KiB
 +
|l1d desc=4-way set associative
 +
|l2 cache=512 KiB
 +
|l2 break=4x128 KiB
 +
|l2 desc=8-way set associative
 +
}}
 +
 +
* 2 MiB L3
  
 
== Memory controller ==
 
== Memory controller ==

Revision as of 23:13, 16 June 2019

Edit Values
Snapdragon 855
sd 855 (front).png
General Info
DesignerQualcomm,
ARM Holdings
ManufacturerTSMC
Model NumberSDM855
Part NumberSM8150
MarketMobile
IntroductionDecember 4, 2018 (announced)
Q1, 2019 (launched)
General Specs
FamilySnapdragon 800
Series800
Frequency1,800 MHz, 2,420 MHz, 2,840 MHz
Microarchitecture
ISAARMv8 (ARM)
MicroarchitectureCortex-A76, Cortex-A55
Core NameKryo 485 Gold, Kryo 485 Silver
Process7 nm
TechnologyCMOS
Die73.27 mm²
8.48 mm × 8.64 mm
Word Size64 bit
Cores8
Threads8
Max Memory16 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Packaging
sd 855 (back).png
Succession
Block Diagram

Snapdragon 855 is a high-performance 64-bit ARM LTE system on a chip designed by Qualcomm and introduced in late 2018. Fabricated on TSMC's 7nm process, the 855 features four Kryo 485 Silver high-efficiency cores operating at 1.8 GHz along with three high-performance Kryo 485 Gold operating at 2.42 GHz and another higher-performance Kryo 485 Gold core operating at 2.84 GHz. The Snapdragon 855 integrates the Adreno 640 GPU operation at ? MHz and features an X24 LTE modem supporting Cat 20 uplink and Cat 20 downlink. This chip supports up to 16 GiB of quad-channel LPDDR4X-4266 memory.

The Snapdragon 855 can be paired with Qualcomm's X50 5G modem (an external chip) and an RF front-end interface chip (RFFE) to bring 5G NR, sub-6 GHz and mmWave, support.

Cache

Main articles: Cortex-A76 § Cache and Cortex-A55 § Cache


1+3 core cluster Cortex-A76:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L2$1 MiB
1,024 KiB
1,048,576 B
9.765625e-4 GiB
  4x256 KiB8-way set associative 

Quad-core cluster Cortex-A55:

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
4x64 KiB2-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
4x64 KiB4-way set associative 
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB8-way set associative 
  • 2 MiB L3

Memory controller

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4266
Supports ECCNo
Max Mem16 GiB
Frequency2133 MHz
Controllers1
Channels8
Width16 bit
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 7.95 GiB/s
Double 15.89 GiB/s
Quad 31.79 GiB/s

DSP

This chip features Qualcomm's Hexagon 685 DSP.

Graphics

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUAdreno 640 GPU
DesignerQualcomm
Max Displays2
Frequency250 MHz
0.25 GHz
250,000 KHz
Burst Frequency585 MHz
0.585 GHz
585,000 KHz
Standards
DirectX12
OpenCL2.0
OpenGL ES3.2
Vulkan1.1
  • Codec: H.265 (HEVC), H.264 (AVC), HDR10, HDR10+, HLG, VP8, VP9
  • HDR Playback Codec support for HDR10+, HDR10, HLG and Dolby Vision
  • Volumetric VR video playback
  • 8K 360 VR video playback

Camera

  • ISP
    • Qualcomm Spectra 380 image signal processor
      • Dual 14-bit CV-ISPs
      • Hardware accelerator for computer vision (CV-ISP)
    • Up to 20 MP dual camera
    • Up to 48 MP single camera
  • Photo Capture: HEIF photo capture
  • Video Capture:
    • Rec. 2020 color gamut video capture
    • Up to 10-bit color depth video capture
    • Slow motion video capture up to 720p at 480fps,HEVC Video Capture

Connectivity

  • X24 LTE modem
    • LTE Category 20
    • Downlink:
      • 2 Gbps peak
      • 7x20 MHz carrier aggregation
      • Up to 256-QAM
      • Up to 4x4 MIMO on five carriers
      • Full-Dimension MIMO (FD-MIMO)
      • Maximum 20 spatial streams
    • Uplink:
      • 316 Mbps peak
      • 3x20 MHz carrier aggregation
      • Up to 2x 106Mbps LTE streams
      • Up to 256-QAM
      • Uplink data compression
  • LTE FDD, LTE TDD including CBRS support, LAA, LTE Broadcast, WCDMA (DB-DC-HSDPA, DC-HSUPA), TD-SCDMA, CDMA 1x, EV-DO, GSM/EDGE
  • WiFi
    • Standards: 802.11ax, 802.11ac Wave 2, 802.11a/b/g, 802.11n
    • Spectral Bands: 2.4 GHz, 5 GHz, 6 GHz
  • Bluetooth
    • Bluetooth 5.0
    • 2 Mbps

Location

  • Systems: GPS, GLONASS, Beidou, Galileo, QZSS, SBAS, Dual frequency GNSS

Documents

Bibliography

Retrieved from "https://en.wikichip.org/w/index.php?title=qualcomm/snapdragon_800/855&oldid=92030"
Facts about "Snapdragon 855 - Qualcomm"
RDF feed
back imageFile:sd 855 (back).png +
base frequency1,800 MHz (1.8 GHz, 1,800,000 kHz) +, 2,420 MHz (2.42 GHz, 2,420,000 kHz) + and 2,840 MHz (2.84 GHz, 2,840,000 kHz) +
core count8 +
core nameKryo 485 Gold + and Kryo 485 Silver +
designerQualcomm + and ARM Holdings +
die area73.27 mm² (0.114 in², 0.733 cm², 73,270,000 µm²) +
die length8.48 mm (0.848 cm, 0.334 in, 8,480 µm) +
die width8.64 mm (0.864 cm, 0.34 in, 8,640 µm) +
dspHexagon 690 DSP +
familySnapdragon 800 +
first announcedDecember 4, 2018 +
first launchedJanuary 2019 +
full page namequalcomm/snapdragon 800/855 +
has ecc memory supportfalse +
instance ofmicroprocessor +
integrated gpuAdreno 640 GPU +
integrated gpu base frequency250 MHz (0.25 GHz, 250,000 KHz) +
integrated gpu designerQualcomm +
integrated gpu max frequency585 MHz (0.585 GHz, 585,000 KHz) +
isaARMv8 +
isa familyARM +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description4-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative + and 2-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size1 MiB (1,024 KiB, 1,048,576 B, 9.765625e-4 GiB) + and 0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateJanuary 2019 +
main imageFile:sd 855 (front).png +
manufacturerTSMC +
market segmentMobile +
max cpu count1 +
max memory16,384 MiB (16,777,216 KiB, 17,179,869,184 B, 16 GiB, 0.0156 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels8 +
microarchitectureCortex-A76 + and Cortex-A55 +
model numberSDM855 +
nameSnapdragon 855 +
part numberSM8150 +
process7 nm (0.007 μm, 7.0e-6 mm) +
series800 +
smp max ways1 +
supported memory typeLPDDR4X-4266 +
technologyCMOS +
thread count8 +
word size64 bit (8 octets, 16 nibbles) +