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Difference between revisions of "intel/microarchitectures/palm cove"
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(→‎Key changes from {{\\|Skylake (Server)}})
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|introduction=2018
 
|introduction=2018
 
|process=10 nm
 
|process=10 nm
 +
|cores=2
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages min=14
 +
|stages max=19
 
|isa=x86-64
 
|isa=x86-64
 +
|extension=MOVBE
 +
|extension 2=MMX
 +
|extension 3=SSE
 +
|extension 4=SSE2
 +
|extension 5=SSE3
 +
|extension 6=SSSE3
 +
|extension 7=SSE4.1
 +
|extension 8=SSE4.2
 +
|extension 9=POPCNT
 +
|extension 10=AVX
 +
|extension 11=AVX2
 +
|extension 12=AES
 +
|extension 13=PCLMUL
 +
|extension 14=FSGSBASE
 +
|extension 15=RDRND
 +
|extension 16=FMA3
 +
|extension 17=F16C
 +
|extension 18=BMI
 +
|extension 19=BMI2
 +
|extension 20=VT-x
 +
|extension 21=VT-d
 +
|extension 22=TXT
 +
|extension 23=TSX
 +
|extension 24=RDSEED
 +
|extension 25=ADCX
 +
|extension 26=PREFETCHW
 +
|extension 27=CLFLUSHOPT
 +
|extension 28=XSAVE
 +
|extension 29=SGX
 +
|extension 30=MPX
 +
|extension 31=AVX-512
 +
|l1i=32 KiB
 +
|l1i per=core
 +
|l1i desc=8-way set associative
 +
|l1d=32 KiB
 +
|l1d per=core
 +
|l1d desc=8-way set associative
 +
|l2=256 KiB
 +
|l2 per=core
 +
|l2 desc=4-way set associative
 +
|l3=2 MiB
 +
|l3 per=core
 +
|l3 desc=16-way set associative
 
|predecessor=Skylake
 
|predecessor=Skylake
 
|predecessor link=intel/microarchitectures/skylake
 
|predecessor link=intel/microarchitectures/skylake
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=== Key changes from {{\\|Skylake (Client)}}===
 
=== Key changes from {{\\|Skylake (Client)}}===
 
* [[10 nm process]] (From [[14 nm]])
 
* [[10 nm process]] (From [[14 nm]])
−
* Core
+
* Front End
 +
** LSD is re-enabled (See {{\\|skylake_(server)#Front-end|Skylake § Front-end}} for details)
 +
** 50% smaller L1 instruction cache 4K page TLB (64-entry, down from 128)
 +
* Back-end
 
** Execution units
 
** Execution units
−
*** New 512-bit FMA unit
+
*** Port 4 now performs 512b stores (from 256b)
 +
*** New 512b FMA unit on Port 0
 
*** New iDIV unit
 
*** New iDIV unit
 +
* Memory subsystem
 +
** Store is now 64B/cycle (from 32B/cycle)
 +
** Load is now 2x64B/cycle (from 2x32B/cycle)
 +
 
{{expand list}}
 
{{expand list}}
  

Revision as of 12:48, 9 May 2019

Edit Values
Palm Cove µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2018
Process10 nm
Core Configs2
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages14-19
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512
Cache
L1I Cache32 KiB/core
8-way set associative
L1D Cache32 KiB/core
8-way set associative
L2 Cache256 KiB/core
4-way set associative
L3 Cache2 MiB/core
16-way set associative
Succession

Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.

Process Technology

Palm Cove is designed to take advantage of Intel's 10 nm process.

Architecture

Key changes from Skylake (Client)

  • 10 nm process (From 14 nm)
  • Front End
    • LSD is re-enabled (See Skylake § Front-end for details)
    • 50% smaller L1 instruction cache 4K page TLB (64-entry, down from 128)
  • Back-end
    • Execution units
      • Port 4 now performs 512b stores (from 256b)
      • New 512b FMA unit on Port 0
      • New iDIV unit
  • Memory subsystem
    • Store is now 64B/cycle (from 32B/cycle)
    • Load is now 2x64B/cycle (from 2x32B/cycle)

This list is incomplete; you can help by expanding it.

New instructions

Cannon Lake introduced a number of new instructions:

Overview

Palm Cove is the core microarchitecture that is found in Intel's Cannon Lake SoCs. Although originally intended to be mass manufactured for all client and server markets, due to Intel's prolong 10 nm process problems, Palm Cove is getting skipped with the exception of a single chip.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/palm_cove&oldid=90663"
Facts about "Palm Cove - Microarchitectures - Intel"
RDF feed
codenamePalm Cove +
core count2 +
designerIntel +
first launched2018 +
full page nameintel/microarchitectures/palm cove +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
namePalm Cove +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +