Difference between revisions of "intel/xeon gold/5217"

	Edit Values
	Xeon Gold 5217
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	5217
Part Number	CD8069504214302
S-Spec	SRFBF
Market	Server
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$1,522.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	5200
Locked	Yes
Frequency	3,000 MHz
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	30
CPUID	0x50655
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	L1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	16
Max Memory	1 TiB
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Electrical
TDP	115 W
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647

Revision as of 01:01, 4 April 2019

Xeon Gold 5217 is a 64-bit octa-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5217 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a turbo boost frequency of up to 3.7 GHz.

Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative	write-back

L2$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		8x1 MiB	16-way set associative	write-back

L3$

11 MiB

11,264 KiB
11,534,336 B
0.0107 GiB

		8x1.375 MiB	11-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	1 TiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: 1x16, x8, x4

@@ Line 75: / Line 75: @@
 |bandwidth qchan=79.47 GiB/s
 |bandwidth hchan=119.21 GiB/s
+}}
+== Expansions ==
+{{expansions main
+|
+{{expansions entry
+|type=PCIe
+|pcie revision=3.0
+|pcie lanes=48
+|pcie config=1x16
+|pcie config 2=x8
+|pcie config 3=x4
+}}
 }}

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5217 - Intel#pcie +
base frequency	3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	30 +
core count	8 +
core family	6 +
core name	Cascade Lake SP +
core stepping	L1 +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon gold/5217 +
has ecc memory support	true +
has locked clock multiplier	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	11-way set associative +
l3$ size	11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
model number	5217 +
name	Xeon Gold 5217 +
package	FCLGA-3647 +
part number	CD8069504214302 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
release price (tray)	$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
s-spec	SRFBF +
series	5200 +
smp max ways	4 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	115 W (115,000 mW, 0.154 hp, 0.115 kW) +
technology	CMOS +
thread count	16 +
word size	64 bit (8 octets, 16 nibbles) +

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Revision as of 01:01, 4 April 2019

Cache

Memory controller

Expansions