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'''Xeon Gold 5217''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5217 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
 
'''Xeon Gold 5217''' is a {{arch|64}} [[octa-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5217 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz.
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== Cache ==
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{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=8x1 MiB
 +
|l2 desc=16-way set associative
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|l2 policy=write-back
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|l3 cache=11 MiB
 +
|l3 break=8x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}

Revision as of 00:49, 4 April 2019

Edit Values
Xeon Gold 5217
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number5217
Part NumberCD8069504214302
S-SpecSRFBF
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$1,522.00 (tray)
ShopAmazon
General Specs
FamilyXeon Gold
Series5200
LockedYes
Frequency3,000 MHz
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier30
CPUID0x50655
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingL1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP4-Way (Multiprocessor)
Electrical
TDP115 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

Xeon Gold 5217 is a 64-bit octa-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5217 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as three UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 3 GHz with a TDP of 115 W and features a turbo boost frequency of up to 3.7 GHz.


Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_gold/5217&oldid=87948"
Facts about "Xeon Gold 5217 - Intel"
RDF feed
base frequency3,000 MHz (3 GHz, 3,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier30 +
core count8 +
core family6 +
core nameCascade Lake SP +
core steppingL1 +
cpuid0x50655 +
designerIntel +
familyXeon Gold +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon gold/5217 +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max cpu count4 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
microarchitectureCascade Lake +
model number5217 +
nameXeon Gold 5217 +
packageFCLGA-3647 +
part numberCD8069504214302 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
release price (tray)$ 1,522.00 (€ 1,369.80, £ 1,232.82, ¥ 157,268.26) +
s-specSRFBF +
series5200 +
smp max ways4 +
socketSocket P + and LGA-3647 +
tdp115 W (115,000 mW, 0.154 hp, 0.115 kW) +
technologyCMOS +
thread count16 +
word size64 bit (8 octets, 16 nibbles) +