Difference between revisions of "intel/xeon gold/6254"

	Edit Values
	Xeon Gold 6254
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	6254
Market	Server
Introduction	December, 2018 (announced); December, 2018 (launched)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6000
Locked	Yes
Frequency	3,100 MHz
Turbo Frequency	4,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	31
CPUID	0x50655
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	18
Threads	36
	Multiprocessing
Max SMP	4-Way (Multiprocessor)
	Packaging
	Template:packages/intel/fclga-3647

Revision as of 19:57, 7 February 2019

Xeon Gold 6254 is a 64-bit 18-core x86 multi-socket high performance server microprocessor set to be introduced by Intel in late 2018. This chip supports up to 4-way multiprocessing. The Gold 6254, which is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm++ process, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor, which operates at 3.1 GHz with a TDP of ? W and a turbo boost frequency of up to 4 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.125 MiB

1,152 KiB
1,179,648 B

L1I$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative
L1D$	576 KiB 589,824 B 0.563 MiB	18x32 KiB	8-way set associative	write-back

L2$

18 MiB

18,432 KiB
18,874,368 B
0.0176 GiB

		18x1 MiB	16-way set associative	write-back

L3$

24.75 MiB

25,344 KiB
25,952,256 B
0.0242 GiB

		18x1.375 MiB	11-way set associative	write-back

Memory controller

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	? GiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions

[Edit/Modify Expansions Info]

Expansion Options

PCIe

Revision	3.0
Max Lanes	48
Configs	x16, x8, x4

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
Run Sure	Run Sure Technology (RAS Capability)
MBE Ctrl	Mode-Based Execute Control
Node Ctrlr	Node Controller Support
DL Boost	Deep Learning Boost

@@ Line 35: / Line 35: @@
 |package module 1={{packages/intel/fclga-3647}}
 }}
-'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor that was supposed to be released in December of 2018, and has yet to be released because Intel sucks donkey nuts. This chip supports up to 4-way multiprocessing. The Gold 6254, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.1 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 4 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory.
+'''Xeon Gold 6254''' is a {{arch|64}} [[18-core]] [[x86]] multi-socket high performance server microprocessor set to be introduced by [[Intel]] in late [[2018]]. This chip supports up to 4-way multiprocessing. The Gold 6254, which is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process|14 nm++ process]], sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor, which operates at 3.1 GHz with a TDP of ? W and a {{intel|turbo boost}} frequency of up to 4 GHz, supports up ? GiB of hexa-channel DDR4-2666 ECC memory.

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 6254 - Intel#io +
base frequency	3,100 MHz (3.1 GHz, 3,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	31 +
core count	18 +
core family	6 +
core name	Cascade Lake SP +
cpuid	0x50655 +
designer	Intel +
family	Xeon Gold +
first announced	December 2018 +
first launched	December 2018 +
full page name	intel/xeon gold/6254 +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,152 KiB (1,179,648 B, 1.125 MiB) +
l1d$ description	8-way set associative +
l1d$ size	576 KiB (589,824 B, 0.563 MiB) +
l1i$ description	8-way set associative +
l1i$ size	576 KiB (589,824 B, 0.563 MiB) +
l2$ description	16-way set associative +
l2$ size	18 MiB (18,432 KiB, 18,874,368 B, 0.0176 GiB) +
l3$ description	11-way set associative +
l3$ size	24.75 MiB (25,344 KiB, 25,952,256 B, 0.0242 GiB) +
ldate	3000 +
main image	+
manufacturer	Intel +
market segment	Server +
max cpu count	4 +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
max pcie lanes	48 +
microarchitecture	Cascade Lake +
model number	6254 +
name	Xeon Gold 6254 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
series	6000 +
smp max ways	4 +
supported memory type	DDR4-2666 +
technology	CMOS +
thread count	36 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

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