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Difference between revisions of "intel/microarchitectures/palm cove"
| Line 22: | Line 22: | ||
* [[10 nm process]] (From [[14 nm]]) | * [[10 nm process]] (From [[14 nm]]) | ||
{{expand list}} | {{expand list}} | ||
| + | |||
| + | ==== New instructions ==== | ||
| + | Cannon Lake introduced a number of {{x86|extensions|new instructions}}: | ||
| + | |||
| + | * {{x86|AVX-512|<code>AVX-512</code>}}, specifically: | ||
| + | ** {{x86|AVX512F|<code>AVX512F</code>}} - AVX-512 Foundation | ||
| + | ** {{x86|AVX512CD|<code>AVX512CD</code>}} - AVX-512 Conflict Detection | ||
| + | ** {{x86|AVX512BW|<code>AVX512BW</code>}} - AVX-512 Byte and Word | ||
| + | ** {{x86|AVX512DQ|<code>AVX512DQ</code>}} - AVX-512 Doubleword and Quadword | ||
| + | ** {{x86|AVX512VL|<code>AVX512VL</code>}} - AVX-512 Vector Length | ||
| + | ** {{x86|AVX512IFMA|<code>AVX512IFMA</code>}} - AVX-512 Integer Fused Multiply-Add | ||
| + | ** {{x86|AVX512VBMI|<code>AVX512VBMI</code>}} - AVX-512 Vector Bit Manipulation | ||
| + | * {{x86|SHA|<code>SHA</code>}} - [[Hardware acceleration]] for SHA hashing operations | ||
| + | * {{x86|UMIP|<code>UMIP</code>}} - User-Mode Instruction Prevention extension | ||
== Overview == | == Overview == | ||
Revision as of 00:38, 30 January 2019
| Edit Values | |
| Palm Cove µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2018 |
| Process | 10 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Palm Cove is a high-performance 10 nm x86 core microarchitecture designed by Intel for an array of server and client products.
Contents
Process Technology
Palm Cove is designed to take advantage of Intel's 10 nm process.
Architecture
Key changes from Skylake (Server)
- 10 nm process (From 14 nm)
This list is incomplete; you can help by expanding it.
New instructions
Cannon Lake introduced a number of new instructions:
-
AVX-512, specifically:-
AVX512F- AVX-512 Foundation -
AVX512CD- AVX-512 Conflict Detection -
AVX512BW- AVX-512 Byte and Word -
AVX512DQ- AVX-512 Doubleword and Quadword -
AVX512VL- AVX-512 Vector Length -
AVX512IFMA- AVX-512 Integer Fused Multiply-Add -
AVX512VBMI- AVX-512 Vector Bit Manipulation
-
-
SHA- Hardware acceleration for SHA hashing operations -
UMIP- User-Mode Instruction Prevention extension
Overview
Palm Cove is the code microarchitecture that is found in Intel's Cannon Lake SoCs. Although originally intended to be mass manufactured for all client and server markets, due to Intel's prolong 10 nm process problems, Palm Cove is getting skipped with the exception of a single chip.
See also
Facts about "Palm Cove - Microarchitectures - Intel"
| codename | Palm Cove + |
| core count | 2 + |
| designer | Intel + |
| first launched | 2018 + |
| full page name | intel/microarchitectures/palm cove + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Palm Cove + |
| pipeline stages (max) | 19 + |
| pipeline stages (min) | 14 + |
| process | 10 nm (0.01 μm, 1.0e-5 mm) + |