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:<math>\text{FLOPS}_\text{system} = \frac{\text{instructions}}{\text{cycle}} \times \frac{\text{operations}}{\text{instruction}} \times \frac{\text{FLOPs}}{\text{operation}} \times \frac{\text{cycles}}{\text{second}} \times \frac{\text{cores}}{\text{node}} \times \frac{\text{nodes}}{\text{system}}</math> | :<math>\text{FLOPS}_\text{system} = \frac{\text{instructions}}{\text{cycle}} \times \frac{\text{operations}}{\text{instruction}} \times \frac{\text{FLOPs}}{\text{operation}} \times \frac{\text{cycles}}{\text{second}} \times \frac{\text{cores}}{\text{node}} \times \frac{\text{nodes}}{\text{system}}</math> | ||
− | == | + | == FLOPs by microarchitecture == |
=== x86 === | === x86 === | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Microarchitecture !! colspan="3" | | + | ! Microarchitecture !! colspan="3" | FLOPs !! ISA |
|- | |- | ||
! colspan="5" | [[Intel]] Microarchitectures | ! colspan="5" | [[Intel]] Microarchitectures | ||
Line 33: | Line 33: | ||
| rowspan="3" | {{intel|Core|l=arch}}<br>{{intel|Penryn|l=arch}}<br>{{intel|Nehalem|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit Multiplication + 1 × 128-bit Addition || rowspan="3" | {{x86|SSE}} (128-bit) | | rowspan="3" | {{intel|Core|l=arch}}<br>{{intel|Penryn|l=arch}}<br>{{intel|Nehalem|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit Multiplication + 1 × 128-bit Addition || rowspan="3" | {{x86|SSE}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 4 | + | | '''DP''' || 4 FLOPs/cycle || 2 FLOPs + 2 FLOPs |
|- | |- | ||
− | | '''SP''' || 8 | + | | '''SP''' || 8 FLOPs/cycle || 4 FLOPs + 4 FLOPs |
|- | |- | ||
| rowspan="3" | {{intel|Sandy Bridge|l=arch}}<br>{{intel|Ivy Bridge|l=arch}} || '''EUs''' || colspan="2" | 1 × 256-bit Multiplication + 1 × 256-bit Addition || rowspan="3" | {{x86|AVX}} (265-bit) | | rowspan="3" | {{intel|Sandy Bridge|l=arch}}<br>{{intel|Ivy Bridge|l=arch}} || '''EUs''' || colspan="2" | 1 × 256-bit Multiplication + 1 × 256-bit Addition || rowspan="3" | {{x86|AVX}} (265-bit) | ||
|- | |- | ||
− | | '''DP''' || 8 | + | | '''DP''' || 8 FLOPs/cycle || 4 FLOPs + 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 16 | + | | '''SP''' || 16 FLOPs/cycle || 8 FLOPs + 8 FLOPs |
|- | |- | ||
| rowspan="3" | {{intel|Haswell|l=arch}}<br>{{intel|Broadwell|l=arch}}<br>{{intel|Skylake|l=arch}}<br>{{intel|Kaby Lake|l=arch}}<br>{{intel|Coffee Lake|l=arch}}<br>{{intel|Whiskey Lake|l=arch}}<br>{{intel|Amber Lake|l=arch}} || '''EUs''' || colspan="2" | 2 × 256-bit FMA || rowspan="3" | {{x86|AVX2}} & FMA (265-bit) | | rowspan="3" | {{intel|Haswell|l=arch}}<br>{{intel|Broadwell|l=arch}}<br>{{intel|Skylake|l=arch}}<br>{{intel|Kaby Lake|l=arch}}<br>{{intel|Coffee Lake|l=arch}}<br>{{intel|Whiskey Lake|l=arch}}<br>{{intel|Amber Lake|l=arch}} || '''EUs''' || colspan="2" | 2 × 256-bit FMA || rowspan="3" | {{x86|AVX2}} & FMA (265-bit) | ||
|- | |- | ||
− | | '''DP''' || 16 | + | | '''DP''' || 16 FLOPs/cycle || 2 × 8 FLOPs |
|- | |- | ||
− | | '''SP''' || 32 | + | | '''SP''' || 32 FLOPs/cycle || 2 × 16 FLOPs |
|- | |- | ||
| rowspan="3" | {{intel|Skylake (server)|l=arch}} || '''EUs''' || colspan="2" | 2 × 512-bit FMA (varies by SKU) || rowspan="3" | {{x86|AVX-512}} & FMA (512-bit) | | rowspan="3" | {{intel|Skylake (server)|l=arch}} || '''EUs''' || colspan="2" | 2 × 512-bit FMA (varies by SKU) || rowspan="3" | {{x86|AVX-512}} & FMA (512-bit) | ||
|- | |- | ||
− | | '''DP''' || 32 | + | | '''DP''' || 32 FLOPs/cycle || 2 × 16 FLOPs |
|- | |- | ||
− | | '''SP''' || 64 | + | | '''SP''' || 64 FLOPs/cycle || 2 × 32 FLOPs |
|- | |- | ||
! colspan="5" | [[Intel]] {{intel|MIC}} Microarchitectures | ! colspan="5" | [[Intel]] {{intel|MIC}} Microarchitectures | ||
Line 59: | Line 59: | ||
| rowspan="3" | {{intel|Knights Landing|l=arch}} || '''EUs''' || colspan="2" | 2 × 512-bit FMA (varies by SKU) || rowspan="3" | {{x86|AVX-512}} & FMA (512-bit) | | rowspan="3" | {{intel|Knights Landing|l=arch}} || '''EUs''' || colspan="2" | 2 × 512-bit FMA (varies by SKU) || rowspan="3" | {{x86|AVX-512}} & FMA (512-bit) | ||
|- | |- | ||
− | | '''DP''' || 32 | + | | '''DP''' || 32 FLOPs/cycle || 2 × 16 FLOPs |
|- | |- | ||
− | | '''SP''' || 64 | + | | '''SP''' || 64 FLOPs/cycle || 2 × 32 FLOPs |
|- | |- | ||
! colspan="5" | [[AMD]] Microarchitectures | ! colspan="5" | [[AMD]] Microarchitectures | ||
Line 67: | Line 67: | ||
| rowspan="3" | {{amd|K10|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit Multiplication + 1 × 128-bit Addition || rowspan="3" | {{x86|SSE}} (128-bit) | | rowspan="3" | {{amd|K10|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit Multiplication + 1 × 128-bit Addition || rowspan="3" | {{x86|SSE}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 4 | + | | '''DP''' || 4 FLOPs/cycle || 2 FLOPs + 2 FLOPs |
|- | |- | ||
− | | '''SP''' || 8 | + | | '''SP''' || 8 FLOPs/cycle || 4 FLOPs + 4 FLOPs |
|- | |- | ||
| rowspan="3" | {{amd|Bulldozer|l=arch}}<br>{{amd|Piledriver|l=arch}}<br>{{amd|Steamroller|l=arch}}<br>{{amd|Excavator|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA (per two cores) || rowspan="3" | {{x86|AVX}} & {{x86|FMA4|FMA}} (128-bit) | | rowspan="3" | {{amd|Bulldozer|l=arch}}<br>{{amd|Piledriver|l=arch}}<br>{{amd|Steamroller|l=arch}}<br>{{amd|Excavator|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA (per two cores) || rowspan="3" | {{x86|AVX}} & {{x86|FMA4|FMA}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 8 | + | | '''DP''' || 8 FLOPs/cycle || 2 x 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 16 | + | | '''SP''' || 16 FLOPs/cycle || 2 x 8 FLOPs |
|- | |- | ||
| rowspan="3" | {{amd|Zen|l=arch}}<br>{{amd|Zen+|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA || rowspan="3" | {{x86|AVX2}} & FMA (128-bit) | | rowspan="3" | {{amd|Zen|l=arch}}<br>{{amd|Zen+|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA || rowspan="3" | {{x86|AVX2}} & FMA (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 8 | + | | '''DP''' || 8 FLOPs/cycle || 2 x 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 16 | + | | '''SP''' || 16 FLOPs/cycle || 2 x 8 FLOPs |
+ | |- | ||
+ | | rowspan="3" | {{amd|Zen 2|l=arch}} || '''EUs''' || colspan="2" | 2 × 256-bit FMA || rowspan="3" | {{x86|AVX2}} & FMA (256-bit) | ||
+ | |- | ||
+ | | '''DP''' || 16 FLOPs/cycle || 2 x 8 FLOPs | ||
+ | |- | ||
+ | | '''SP''' || 32 FLOPs/cycle || 2 x 16 FLOPs | ||
|} | |} | ||
Line 87: | Line 93: | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
− | ! Microarchitecture !! colspan="3" | | + | ! Microarchitecture !! colspan="3" | FLOPs !! ISA |
|- | |- | ||
! colspan="5" | [[ARM]] Microarchitectures | ! colspan="5" | [[ARM]] Microarchitectures | ||
Line 93: | Line 99: | ||
| rowspan="3" | {{armh|Cortex-A57|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | | rowspan="3" | {{armh|Cortex-A57|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 4 | + | | '''DP''' || 4 FLOPs/cycle || 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 8 | + | | '''SP''' || 8 FLOPs/cycle || 8 FLOPs |
|- | |- | ||
! colspan="5" | [[AppliedMicro]]/[[Ampere Computing]] Microarchitectures | ! colspan="5" | [[AppliedMicro]]/[[Ampere Computing]] Microarchitectures | ||
Line 101: | Line 107: | ||
| rowspan="3" | {{apm|Storm|l=arch}}<br>{{arm|Shadowcat|l=arch}}<br>{{arm|Skylark|l=arch}} || '''EUs''' || colspan="2" | 1 × 64-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | | rowspan="3" | {{apm|Storm|l=arch}}<br>{{arm|Shadowcat|l=arch}}<br>{{arm|Skylark|l=arch}} || '''EUs''' || colspan="2" | 1 × 64-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 2 | + | | '''DP''' || 2 FLOPs/cycle || 2 FLOPs |
|- | |- | ||
− | | '''SP''' || 4 | + | | '''SP''' || 4 FLOPs/cycle || 4 FLOPs |
|- | |- | ||
! colspan="5" | [[Cavium]] Microarchitectures | ! colspan="5" | [[Cavium]] Microarchitectures | ||
Line 109: | Line 115: | ||
| rowspan="3" | {{cavium|Vulcan|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | | rowspan="3" | {{cavium|Vulcan|l=arch}} || '''EUs''' || colspan="2" | 2 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 8 | + | | '''DP''' || 8 FLOPs/cycle || 2 x 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 16 | + | | '''SP''' || 16 FLOPs/cycle || 2 x 8 FLOPs |
|- | |- | ||
! colspan="5" | [[Samsung]] Microarchitectures | ! colspan="5" | [[Samsung]] Microarchitectures | ||
Line 117: | Line 123: | ||
| rowspan="3" | {{samsung|M1|l=arch}}<br>{{samsung|M2|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit FMA + 1 × 128-bit Addition || rowspan="3" | {{arm|ARMv8}} (128-bit) | | rowspan="3" | {{samsung|M1|l=arch}}<br>{{samsung|M2|l=arch}} || '''EUs''' || colspan="2" | 1 × 128-bit FMA + 1 × 128-bit Addition || rowspan="3" | {{arm|ARMv8}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 6 | + | | '''DP''' || 6 FLOPs/cycle || 1 x 4 FLOPs + 1 x 2 FLOPs |
|- | |- | ||
− | | '''SP''' || 12 | + | | '''SP''' || 12 FLOPs/cycle || 1 x 8 FLOPs + 1 x 4 FLOPs |
|- | |- | ||
| rowspan="3" | {{samsung|M3|l=arch}} || '''EUs''' || colspan="2" | 3 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | | rowspan="3" | {{samsung|M3|l=arch}} || '''EUs''' || colspan="2" | 3 × 128-bit FMA || rowspan="3" | {{arm|ARMv8}} (128-bit) | ||
|- | |- | ||
− | | '''DP''' || 12 | + | | '''DP''' || 12 FLOPs/cycle || 3 x 4 FLOPs |
|- | |- | ||
− | | '''SP''' || 24 | + | | '''SP''' || 24 FLOPs/cycle || 3 x 8 FLOPs |
|} | |} | ||
Revision as of 14:06, 18 November 2018
Floating-point operations per second (FLOPS) is a microprocessor performance unit used to quantify the number of floating-point operations a core, machine, or system is capable of in a one second.
Overview
FLOPS are a measure of performance used for comparing the peak theoretical performance of a core, microprocessor, or system using floating point operations. This unit is often used in the field of high-performance computing (e.g., supercomputers) in order to evaluate the peak theoretical performance of various scientific workloads. Traditionally, the FLOPS of a microprocessor could be calculated using the following equation:
With the advent of multi-socket and multi-core architectures, additional levels of explicit parallelism have been introduced resulting in the following modified equation:
and,
Modern microprocessors exploit data parallelism further through the introduction of various vector extensions such as x86's AVX and ARM's SVE. With those extensions, it's possible to perform multiple floating-point operations within a single instruction. For example, a typical fused multiply-accumulate (FMAC) operation can perform two floating-point operations at once. For a single core, this can be expressed as
And for a full system, this can be extended to:
FLOPs by microarchitecture
x86
Microarchitecture | FLOPs | ISA | ||
---|---|---|---|---|
Intel Microarchitectures | ||||
Core Penryn Nehalem |
EUs | 1 × 128-bit Multiplication + 1 × 128-bit Addition | SSE (128-bit) | |
DP | 4 FLOPs/cycle | 2 FLOPs + 2 FLOPs | ||
SP | 8 FLOPs/cycle | 4 FLOPs + 4 FLOPs | ||
Sandy Bridge Ivy Bridge |
EUs | 1 × 256-bit Multiplication + 1 × 256-bit Addition | AVX (265-bit) | |
DP | 8 FLOPs/cycle | 4 FLOPs + 4 FLOPs | ||
SP | 16 FLOPs/cycle | 8 FLOPs + 8 FLOPs | ||
Haswell Broadwell Skylake Kaby Lake Coffee Lake Whiskey Lake Amber Lake |
EUs | 2 × 256-bit FMA | AVX2 & FMA (265-bit) | |
DP | 16 FLOPs/cycle | 2 × 8 FLOPs | ||
SP | 32 FLOPs/cycle | 2 × 16 FLOPs | ||
Skylake (server) | EUs | 2 × 512-bit FMA (varies by SKU) | AVX-512 & FMA (512-bit) | |
DP | 32 FLOPs/cycle | 2 × 16 FLOPs | ||
SP | 64 FLOPs/cycle | 2 × 32 FLOPs | ||
Intel MIC Microarchitectures | ||||
Knights Landing | EUs | 2 × 512-bit FMA (varies by SKU) | AVX-512 & FMA (512-bit) | |
DP | 32 FLOPs/cycle | 2 × 16 FLOPs | ||
SP | 64 FLOPs/cycle | 2 × 32 FLOPs | ||
AMD Microarchitectures | ||||
K10 | EUs | 1 × 128-bit Multiplication + 1 × 128-bit Addition | SSE (128-bit) | |
DP | 4 FLOPs/cycle | 2 FLOPs + 2 FLOPs | ||
SP | 8 FLOPs/cycle | 4 FLOPs + 4 FLOPs | ||
Bulldozer Piledriver Steamroller Excavator |
EUs | 2 × 128-bit FMA (per two cores) | AVX & FMA (128-bit) | |
DP | 8 FLOPs/cycle | 2 x 4 FLOPs | ||
SP | 16 FLOPs/cycle | 2 x 8 FLOPs | ||
Zen Zen+ |
EUs | 2 × 128-bit FMA | AVX2 & FMA (128-bit) | |
DP | 8 FLOPs/cycle | 2 x 4 FLOPs | ||
SP | 16 FLOPs/cycle | 2 x 8 FLOPs | ||
Zen 2 | EUs | 2 × 256-bit FMA | AVX2 & FMA (256-bit) | |
DP | 16 FLOPs/cycle | 2 x 8 FLOPs | ||
SP | 32 FLOPs/cycle | 2 x 16 FLOPs |
ARM
Microarchitecture | FLOPs | ISA | ||
---|---|---|---|---|
ARM Microarchitectures | ||||
Cortex-A57 | EUs | 1 × 128-bit FMA | ARMv8 (128-bit) | |
DP | 4 FLOPs/cycle | 4 FLOPs | ||
SP | 8 FLOPs/cycle | 8 FLOPs | ||
AppliedMicro/Ampere Computing Microarchitectures | ||||
Storm Shadowcat Skylark |
EUs | 1 × 64-bit FMA | ARMv8 (128-bit) | |
DP | 2 FLOPs/cycle | 2 FLOPs | ||
SP | 4 FLOPs/cycle | 4 FLOPs | ||
Cavium Microarchitectures | ||||
Vulcan | EUs | 2 × 128-bit FMA | ARMv8 (128-bit) | |
DP | 8 FLOPs/cycle | 2 x 4 FLOPs | ||
SP | 16 FLOPs/cycle | 2 x 8 FLOPs | ||
Samsung Microarchitectures | ||||
M1 M2 |
EUs | 1 × 128-bit FMA + 1 × 128-bit Addition | ARMv8 (128-bit) | |
DP | 6 FLOPs/cycle | 1 x 4 FLOPs + 1 x 2 FLOPs | ||
SP | 12 FLOPs/cycle | 1 x 8 FLOPs + 1 x 4 FLOPs | ||
M3 | EUs | 3 × 128-bit FMA | ARMv8 (128-bit) | |
DP | 12 FLOPs/cycle | 3 x 4 FLOPs | ||
SP | 24 FLOPs/cycle | 3 x 8 FLOPs |