Revision as of 23:30, 23 October 2018

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Core i9-9900X
General Info
Designer	Intel
Manufacturer	Intel
Model Number	i9-9900X
Part Number	BX80673I99900X, BXC80673I99900X
Market	Desktop
Introduction	October 8, 2018 (announced) November, 2018 (launched)
Release Price	$989 (tray)
Shop	Amazon
General Specs
Family	Core i9
Series	i9-9000
Locked	No
Frequency	3,500 MHz
Turbo Frequency	4,400 MHz (1 core), 4,400 MHz (2 cores)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	35
Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Skylake (server)
Platform	Basin Falls Refresh
Chipset	Lewisburg
Core Name	Skylake X Refresh
Core Family	6
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	10
Threads	20
Max Memory	128 GiB
Multiprocessing
Max SMP	1-Way (Uniprocessor)
Electrical
TDP	165 W
Tjunction	0 °C – 92 °C
Tstorage	-25 °C – 125 °C
Packaging
Template:packages/intel/lga-2066

Core i9-9900X is a 64-bit deca-core high-performance x86 desktop microprocessor introduced by Intel in late 2018. This chip, which is based on the Skylake microarchitecture, is fabricated on Intel's 14 nm process. The i9-9900X operates at 3.5 GHz with a TDP of 165 W and a Turbo Boost frequency of up to 4.4 GHz. The processor supports up to 128 GiB of quad-channel DDR4-2666 memory.

In addition to its Turbo Boost frequency, the i9-9900X has a Turbo Max frequency of 4.5 GHz.

Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.

Cache

Main article: Skylake § Cache

[Edit/Modify Cache Info]

Cache Organization Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes.

L1$ 640 KiB 655,360 B 0.625 MiB L1I$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative   L1D$ 320 KiB 327,680 B 0.313 MiB 10x32 KiB 8-way set associative write-back L2$ 10 MiB 10,240 KiB 10,485,760 B 0.00977 GiB     10x1 MiB 16-way set associative write-back L3$ 19.25 MiB 19,712 KiB 20,185,088 B 0.0188 GiB     14x1.375 MiB 11-way set associative write-back

Memory controller

[Edit/Modify Memory Info]

	Integrated Memory Controller
	Max Type DDR4-2666 Supports ECC No Max Mem 128 GiB Channels 4 Max Bandwidth 79.47 GiB/s 81,377.28 MiB/s 85.33 GB/s 85,330.263 MB/s 0.0776 TiB/s 0.0853 TB/s Bandwidth Single 19.89 GiB/s Double 39.72 GiB/s Quad 79.47 GiB/s

Expansions

[Edit/Modify Expansions Info]

	Expansion Options
PCIe Revision: 3.0 Max Lanes: 44 Configuration: x16, x8, x4

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX MMX Extension EMMX Extended MMX Extension SSE Streaming SIMD Extensions SSE2 Streaming SIMD Extensions 2 SSE3 Streaming SIMD Extensions 3 SSSE3 Supplemental SSE3 SSE4.1 Streaming SIMD Extensions 4.1 SSE4.2 Streaming SIMD Extensions 4.2 AVX Advanced Vector Extensions AVX2 Advanced Vector Extensions 2 AVX-512 Advanced Vector 512-bit (2 Units) AVX512F AVX-512 Foundation AVX512CD AVX-512 Conflict Detection AVX512BW AVX-512 Byte and Word AVX512DQ AVX-512 Doubleword and Quadword Instructions AVX512VL AVX-512 Vector Length ABM Advanced Bit Manipulation BMI1 Bit Manipulation Instruction Set 1 BMI2 Bit Manipulation Instruction Set 2 FMA3 3-Operand Fused-Multiply-Add AES AES Encryption Instructions RdRand Hardware RNG ADX Multi-Precision Add-Carry CLMUL Carry-less Multiplication Extension F16C 16-bit Floating Point Conversion x86-16 16-bit x86 x86-32 32-bit x86 x86-64 64-bit x86 Real Real Mode Protected Protected Mode SMM System Management Mode FPU Integrated x87 FPU NX No-eXecute HT Hyper-Threading TBT 2.0 Turbo Boost Technology 2.0 TBMT 3.0 Turbo Boost Max Technology 3.0 EIST Enhanced SpeedStep Technology VT-x VT-x (Virtualization) VT-d VT-d (I/O MMU virtualization) TSX Transactional Synchronization Extensions