Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "zhaoxin/microarchitectures/zhangjiang"
(→New instructions) |
|||
| Line 32: | Line 32: | ||
== Process Technology == | == Process Technology == | ||
| − | + | ZhangJiang is manufactured on [[HLMC]]'s [[28 nm process]]. | |
== Architecture == | == Architecture == | ||
Latest revision as of 20:12, 15 September 2021
| Edit Values | |
| ZhangJiang µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Zhaoxin |
| Manufacturer | TSMC |
| Introduction | 2015 |
| Process | 28 nm |
| Core Configs | 2, 4, 8 |
| Pipeline | |
| Type | Superscalar |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Succession | |
ZhangJiang is the successor to Isaiah II, a 28 nm x86 microarchitecture designed by Zhaoxin for mainstream laptops, desktops, and servers.
Contents
Brands[edit]
| Family | Series | Description |
|---|---|---|
| KaiXian | C/C+ (4000) | Desktop, Laptops |
| Kaisheng | C+ (4000) | Storage, Servers |
Process Technology[edit]
ZhangJiang is manufactured on HLMC's 28 nm process.
Architecture[edit]
It is believed that this architecture is largely based on VIA's Isaiah II.
Key changes from Isaiah II[edit]
This list is incomplete; you can help by expanding it.
New instructions[edit]
ZhangJiang introduced a number of new instructions:
-
SM3- Hardware acceleration for SM3 hashing operations -
SM4- Hardware acceleration for SM4 hashing operations
Die[edit]
- TSMC's 28 nm process
- 300,000,000 transistors
Facts about "ZhangJiang - Microarchitectures - Zhaoxin"
| codename | ZhangJiang + |
| core count | 2 +, 4 + and 8 + |
| designer | Zhaoxin + |
| first launched | 2015 + |
| full page name | zhaoxin/microarchitectures/zhangjiang + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | ZhangJiang + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |