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Difference between revisions of "greenwaves/gap8"
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'''GAP8''' is a [[nona-core]] {{arch|32}} [[RISC-V]] ultra-low power microprocessor designed by [[GreenWaves]] and introduced in early [[2018]] for the edge computing and IoT market. This processor, which is fabricated on [[TSMC]]'s [[55nm process|55LP process]], is based on the {{ethz|PULP}} open core.
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'''GAP8''' is a [[nona-core]] {{arch|32}} [[RISC-V]] ultra-low power microprocessor designed by [[GreenWaves]] and introduced in early [[2018]] for the edge computing and IoT market. This processor, which is fabricated on [[TSMC]]'s [[55nm process|55LP process]], is based on the {{ethz|PULP}} open core. The GAP8 incorporates [[9 cores|nine]] RISC-V cores along with a [[neural process]] designed to accelerate [[convolutional neural network]]s (CNN). The GAP8 is said to offer a peak performance of up to 200 MOPS at 1 mW and up to 10 GOPS at a few tens of mW, making it well suitable for long autonomous battery-powered life.
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== Overview ==
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:[[File:gap8 block diagram.svg|700px]]
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== Cache ==
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The GAP8 a private L1 cache for the MCU core which consists of a 16 KiB of data cache and 4 KiB of instruction cache. The compute engine has a shared level 1 cache of its own which consists of a 16 KiB instruction cache and a 64 KiB data cache. Additional, the entire chip shares a 512 KiB level 2 cache consisting of 4 128 KiB cache banks.
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{{cache size
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|l1 cache=100 KiB
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|l1i cache=20 KiB
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|l1i break=16 KiB + 4 KiB
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|l1d cache=80 KiB
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|l1d break=64 KiB + 16 KiB
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|l2 cache=512 KiB
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|l2 break=4x128 KiB
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}}
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== Memory ==
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The chip supports up to 16 MiB of SDRAM or additional RAM through the HyperBus interface.
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== Expansions ==
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* 128 Mb/s [[LVDS]] IEEE compliant
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* Serial I/Q
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* [[UART]]
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* Quad SPI Master + additional SPI Master
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* [[SPI]] Slave
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* [[I2S]] (2)
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* [[I2C]] (2)
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* Camera parallel interface (CPI)
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* HyperBus (External Flash and RAM)
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* 32 x GPIOs
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== Features ==
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* 4x PWM
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* 32 kHz external quartz
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* Programmable Voltage Regulator
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* Real Time Clock
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* 2 programmable clocks
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* Secured execution support with Memory Protection Unit (MPU)
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== See also ==
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* <!-- [https://fuse.wikichip.org/news/990/the-risc-v-momentum-continues-with-the-gap8-an-iot-ai-application-processor/ GAP8 on WikiChip Fuse]-->

Revision as of 02:05, 28 February 2018

Edit Values
GAP8
greenwaves gap8 (front).png
GAP8, front package
General Info
DesignerGreenWaves
ManufacturerTSMC
Model NumberGAP8
MarketEmbedded
IntroductionOctober, 2016 (announced)
February 26, 2018 (launched)
Release Price$5
General Specs
Frequency250 MHz
Microarchitecture
ISARV32IMC (RISC-V)
Process55 nm
TechnologyCMOS
Word Size32 bit
Cores9
Threads9
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Power dissipation60 mW
Vcore1 V-1.2 V
VI/O1.8 V, 3.3 V
Packaging
PackageaQFN-84
(Advanced QFN)		greenwaves gap8 (back).png
Contacts1288

GAP8 is a nona-core 32-bit RISC-V ultra-low power microprocessor designed by GreenWaves and introduced in early 2018 for the edge computing and IoT market. This processor, which is fabricated on TSMC's 55LP process, is based on the PULP open core. The GAP8 incorporates nine RISC-V cores along with a neural process designed to accelerate convolutional neural networks (CNN). The GAP8 is said to offer a peak performance of up to 200 MOPS at 1 mW and up to 10 GOPS at a few tens of mW, making it well suitable for long autonomous battery-powered life.

Overview

gap8 block diagram.svg

Cache

The GAP8 a private L1 cache for the MCU core which consists of a 16 KiB of data cache and 4 KiB of instruction cache. The compute engine has a shared level 1 cache of its own which consists of a 16 KiB instruction cache and a 64 KiB data cache. Additional, the entire chip shares a 512 KiB level 2 cache consisting of 4 128 KiB cache banks.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$100 KiB
102,400 B
0.0977 MiB
L1I$20 KiB
20,480 B
0.0195 MiB
16 KiB + 4 KiB  
L1D$80 KiB
81,920 B
0.0781 MiB
64 KiB + 16 KiB  
L2$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
  4x128 KiB  

Memory

The chip supports up to 16 MiB of SDRAM or additional RAM through the HyperBus interface.

Expansions

  • 128 Mb/s LVDS IEEE compliant
  • Serial I/Q
  • UART
  • Quad SPI Master + additional SPI Master
  • SPI Slave
  • I2S (2)
  • I2C (2)
  • Camera parallel interface (CPI)
  • HyperBus (External Flash and RAM)
  • 32 x GPIOs

Features

  • 4x PWM
  • 32 kHz external quartz
  • Programmable Voltage Regulator
  • Real Time Clock
  • 2 programmable clocks
  • Secured execution support with Memory Protection Unit (MPU)


See also

Retrieved from "https://en.wikichip.org/w/index.php?title=greenwaves/gap8&oldid=74560"
Facts about "GAP8 - GreenWaves"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
GAP8 - GreenWaves#package +
base frequency250 MHz (0.25 GHz, 250,000 kHz) +
core count9 +
core voltage (max)1.2 V (12 dV, 120 cV, 1,200 mV) +
core voltage (min)1 V (10 dV, 100 cV, 1,000 mV) +
designerGreenWaves +
first announcedOctober 2016 +
first launchedFebruary 26, 2018 +
full page namegreenwaves/gap8 +
instance ofmicroprocessor +
io voltage1.8 V (18 dV, 180 cV, 1,800 mV) + and 3.3 V (33 dV, 330 cV, 3,300 mV) +
isaRV32IMC +
isa familyRISC-V +
l1$ size100 KiB (102,400 B, 0.0977 MiB) +
l1d$ size80 KiB (81,920 B, 0.0781 MiB) +
l1i$ size20 KiB (20,480 B, 0.0195 MiB) +
l2$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
ldateFebruary 26, 2018 +
main imageFile:greenwaves gap8 (front).png +
main image captionGAP8, front package +
manufacturerTSMC +
market segmentEmbedded +
max cpu count1 +
model numberGAP8 +
nameGAP8 +
packageaQFN +
power dissipation0.06 W (60 mW, 8.046e-5 hp, 6.0e-5 kW) +
process55 nm (0.055 μm, 5.5e-5 mm) +
release price$ 5.00 (€ 4.50, £ 4.05, ¥ 516.65) +
smp max ways1 +
technologyCMOS +
thread count9 +
word size32 bit (4 octets, 8 nibbles) +