From WikiChip
Difference between revisions of "zhaoxin/kaisheng/kh-26800"
< zhaoxin‎ | kaisheng

(KH-26800)
 
(→‎Expansions)
 
Line 74: Line 74:
 
|pcie revision=3.0
 
|pcie revision=3.0
 
|pcie lanes=24
 
|pcie lanes=24
−
|pcie config=x16
 
−
|pcie config 2=x8
 
−
|pcie config 3=x4
 
 
}}
 
}}
 
}}
 
}}

Latest revision as of 23:51, 30 January 2018

Edit Values
KaisHeng KH-26800
KH-26800.png
KH-26800 front
General Info
DesignerZhaoxin
ManufacturerHLMC
Model NumberKH-26800
Part NumberKH-26800
MarketServer, Networking, Embedded
IntroductionDecember 28, 2017 (announced)
December 28, 2017 (launched)
General Specs
FamilyKaisHeng
SeriesKH-20000
Frequency2,000 MHz
Bus typePCIe 3.0
Bus rate4 × 8 GT/s
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureWuDaoKou
Process28 nm
Transistors2,100,000,000
TechnologyCMOS
Die187 mm²
Word Size64 bit
Cores8
Threads8
Max Memory128 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
Tjunction0 °C – 90 °C

KaisHeng KH-26800 is a 64-bit octa-core x86 microprocessor designed by Zhaoxin and introduced in late 2017 specifically for the Chinese market. This processor is fabricated on a 28 nm process based on the WuDaoKou microarchitecture. The KH-26800 operates at 2 GHz with a TDP of ? W and supports up to 128 GiB of dual-channel DDR4-2133 ECC memory.


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache[edit]

Main article: WuDaoKou § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  2x4 MiB32-way set associative 

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2133
Supports ECCYes
Max Mem128 GiB
Controllers1
Channels2
Max Bandwidth31.79 GiB/s
32,552.96 MiB/s
34.134 GB/s
34,134.253 MB/s
0.031 TiB/s
0.0341 TB/s
Bandwidth
Single 15.89 GiB/s
Double 31.79 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 24


Features[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=zhaoxin/kaisheng/kh-26800&oldid=73283"
Facts about "KaisHeng KH-26800 - Zhaoxin"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
KaisHeng KH-26800 - Zhaoxin#pcie +
base frequency2,000 MHz (2 GHz, 2,000,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typePCIe 3.0 +
core count8 +
designerZhaoxin +
die area187 mm² (0.29 in², 1.87 cm², 187,000,000 µm²) +
familyKaisHeng +
first announcedDecember 28, 2017 +
first launchedDecember 28, 2017 +
full page namezhaoxin/kaisheng/kh-26800 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Extended Page Tables +, Intel VT-x + and Trusted Execution Technology +
has intel trusted execution technologytrue +
has intel vt-x technologytrue +
has second level address translation supporttrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description32-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
ldateDecember 28, 2017 +
main imageFile:KH-26800.png +
main image captionKH-26800 front +
manufacturerHLMC +
market segmentEmbedded +, Networking + and Server +
max cpu count1 +
max junction temperature363.15 K (90 °C, 194 °F, 653.67 °R) +
max memory131,072 MiB (134,217,728 KiB, 137,438,953,472 B, 128 GiB, 0.125 TiB) +
max memory bandwidth31.79 GiB/s (32,552.96 MiB/s, 34.134 GB/s, 34,134.253 MB/s, 0.031 TiB/s, 0.0341 TB/s) +
max memory channels2 +
microarchitectureWuDaoKou +
min junction temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model numberKH-26800 +
nameKaisHeng KH-26800 +
part numberKH-26800 +
process28 nm (0.028 μm, 2.8e-5 mm) +
seriesKH-20000 +
smp max ways1 +
supported memory typeDDR4-2133 +
technologyCMOS +
thread count8 +
transistor count2,100,000,000 +
word size64 bit (8 octets, 16 nibbles) +