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Difference between revisions of "nervana/microarchitectures/lake crest"
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== Architecture == | == Architecture == | ||
| + | * Tensor-based architecture | ||
| + | ** Nervana Engine | ||
| + | * [[Flexpoint]] number format | ||
| + | * HBM2 memory | ||
| + | {{expand list}} | ||
| + | |||
| + | === Block Diagram === | ||
{{empty section}} | {{empty section}} | ||
| + | |||
| + | === Memory Hierarchy === | ||
| + | * 32 GiB on-package [[HBM2]] | ||
| + | ** 1 TiB/s | ||
Revision as of 02:31, 29 December 2017
| Edit Values | |
| Lake Crest µarch | |
| General Info | |
| Arch Type | NPU |
| Designer | Nervana |
| Manufacturer | TSMC |
| Process | 28 nm |
| Succession | |
Lake Crest is a neural processor microarchitecture designed by Nervana.
Process Technology
Lake Crest is fabricated on TSMC's 28 nm process.
Architecture
- Tensor-based architecture
- Nervana Engine
- Flexpoint number format
- HBM2 memory
This list is incomplete; you can help by expanding it.
Block Diagram
 |
This section is empty; you can help add the missing info by editing this page. |
Memory Hierarchy
- 32 GiB on-package HBM2
- 1 TiB/s
Facts about "Lake Crest - Microarchitectures - Intel Nervana"
| codename | Lake Crest + |
| designer | Nervana + |
| full page name | nervana/microarchitectures/lake crest + |
| instance of | microarchitecture + |
| manufacturer | TSMC + |
| name | Lake Crest + |
| process | 28 nm (0.028 μm, 2.8e-5 mm) + |