From WikiChip
Difference between revisions of "intel/xeon w/w-2150b"
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Revision as of 23:48, 23 December 2017
Edit Values | |
Xeon W-2150B | |
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General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-2150B |
Market | Workstation |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-2000 |
Locked | Yes |
Frequency | 3,000 MHz |
Turbo Frequency | 4,500 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 30 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Skylake (server) |
Platform | Purley |
Core Name | Skylake W |
Core Family | 6 |
Core Stepping | U0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 10 |
Threads | 20 |
Max Memory | 512 GiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
Tcase | 0 °C – 68 °C |
Packaging | |
Template:packages/intel/fclga-2066 |
W-2150B is a 64-bit deca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2017. This processors, which is fabricated on an enhanced 14nm+ process based on the Skylake server microarchitecture, operates at 3.0 GHz with a TDP of ? W and a turbo boost frequency of up to ? GHz. This chip supports up to 512 GiB of quad-channel DDR4-2666 ECC memory.
This specific model appears to be a special model for Apple for their iMac Pros.
Contents
Cache
- Main article: Skylake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller
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Integrated Memory Controller
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Expansions
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Expansion Options |
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Features
[Edit/Modify Supported Features]
Facts about "Xeon W-2150B - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-2150B - Intel#pcie + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
max memory bandwidth | 79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) + |
max memory channels | 4 + |
number of avx-512 execution units | 2 + |
supported memory type | DDR4-2666 + |
x86/has memory protection extensions | true + |