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Difference between revisions of "intel/microarchitectures/cannon lake"
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{{intel title|Cannonlake|arch}}
 
{{intel title|Cannonlake|arch}}
 
{{microarchitecture
 
{{microarchitecture
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| atype           = CPU
+
|atype=CPU
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| name             = Cannonlake
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|name=Cannonlake
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| designer         = Intel
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|designer=Intel
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| manufacturer     = Intel
+
|manufacturer=Intel
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| introduction     = 2017
+
|introduction=2017
−
| phase-out        =
+
|process=10 nm
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| process         = 10 nm
+
|core name=Cannonlake Y
−
 
+
|core name 2=Cannonlake U
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| core names      = Yes
+
|predecessor=Kaby Lake
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| core name       = Cannonlake Y
+
|predecessor link=intel/microarchitectures/kaby lake
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| core name 2     = Cannonlake U
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|successor=Ice Lake
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| core name 3      =
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|successor link=intel/microarchitectures/ice lake
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| core name 4      =
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|core names=Yes
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| core name 5      =
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|succession=Yes
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| core name 6      =
 
−
 
 
−
| succession      = Yes
 
−
| predecessor     = Kaby Lake
 
−
| predecessor link = intel/microarchitectures/kaby lake
 
−
| successor       = Icelake
 
−
| successor link   = intel/microarchitectures/icelake
 
 
}}
 
}}
 
'''Cannonlake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannonlake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.
 
'''Cannonlake''' ('''CNL''') (formerly '''Skymont''') is a planned [[microarchitecture]] by [[Intel]] as a successor to {{\\|Kaby Lake}}. Cannonlake is expected to be fabricated using a [[10 nm process]] and is set to be introduced in the fourth quarter of [[2017]]. Cannonlake is the "Process" microarchitecture as part of Intel's {{intel|PAO}} model.

Revision as of 15:35, 24 November 2017

Edit Values
Cannonlake µarch
General Info
Arch TypeCPU
DesignerIntel
ManufacturerIntel
Introduction2017
Process10 nm
Cores
Core NamesCannonlake Y,
Cannonlake U
Succession

Cannonlake (CNL) (formerly Skymont) is a planned microarchitecture by Intel as a successor to Kaby Lake. Cannonlake is expected to be fabricated using a 10 nm process and is set to be introduced in the fourth quarter of 2017. Cannonlake is the "Process" microarchitecture as part of Intel's PAO model.

For mobile, Cannonlake is expected to be branded as 8th Generation Intel Core i3, Core i5. and Core i7 processors.

Process Technology

Cannonlake is manufactured on Intel's 10 nm process (P1274). Intel's 10 nm process is the first high-volume manufacturing process to employ Self-Aligned Quad Patterning (SAQP) (goes under the "Hyper-Scaling" marketing name). Intel's 10nm features a 0.0367 µm² SRAM bit cell.

Scaling:

Broadwell Cannonlake Δ intel 10nm fin.png
14 nm 10 nm
Fin Pitch 42 nm 34 0.81x
Fin Width​ 8 nm  ? nm  ?x
Fin Height​ 42 nm 53 nm 1.24x
Gate Pitch 70 nm 54 nm 0.77x
Interconnect Pitch 52 nm 36 nm 0.69x
Cell Height 399 nm 272 nm 0.68x

Codenames

Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core Abbrev Description Graphics Target
Cannonlake Y CNL-Y Extremely low power GT2 2-in-1s detachable, tablets, and computer sticks
Cannonlake U CNL-U Ultra-low Power GT2/GT3 Light notebooks, portable All-in-Ones (AiOs), Minis, and conference room
Cannonlake H CNL-H High-performance Graphics GT2/GT3 Ultimate mobile performance, mobile workstations
Cannonlake S CNL-S Performance-optimized lifestyle GT2/GT3 Desktop performance to value, AiOs, and minis
Cannonlake DT CNL-DT Workstation GT2 Workstations & entry-level servers

Architecture

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Key changes from Kaby Lake

  • 10 nm process (from 14 nm)
  • Mainstream chipset
    • 200 Series chipset → 300 Series chipset
      • Integrated Programmable (Open FW SDK) Quad-Core Audio DSP
      • Soundwire Digital Audio Interface
      • Integrated USB 3.1 (10 Gib/s)
        • Up to 6 ports
      • Integrated Intel wireless controller (IEEE 802.11ac)
      • Integrated SDXC 3.0 controller
      • Thunderbolt 3.0(Titan Ridge) with DisplayPort 1.4 support
      • C10 & S0ix Support for Modern Standby

All Cannonlake Chips

 Cannonlake Chips
 Main processorIGPMajor Feature Diff
ModelLaunchedPriceFamilyPlatformCoreCTL3$L4$TDPFreqTurboMax MemNameFreqTurboTBTHTAVX2TXTTSXvProVT-d
 Uniprocessors
 No Cannonlake Chips have been released yet.
Count: 0

References

  • Mark Bohr, Intel. Intel Technology and Manufacturing Day. Mar 28, 2017.

See also

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/microarchitectures/cannon_lake&oldid=67748"
Facts about "Cannon Lake - Microarchitectures - Intel"
RDF feed
codenameCannon Lake +
core count2 +
designerIntel +
first launchedMay 15, 2018 +
full page nameintel/microarchitectures/cannon lake +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerIntel +
microarchitecture typeCPU +
nameCannon Lake +
pipeline stages (max)19 +
pipeline stages (min)14 +
process10 nm (0.01 μm, 1.0e-5 mm) +