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Difference between revisions of "acorn/microarchitectures/arm3"
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'''ARM3''' is the second-generation commercial [[ARM]] implementation designed by [[ARM Holdings]] (then [[Acorn Computers]]) as a successor to the {{\\|ARM2}}.
 
'''ARM3''' is the second-generation commercial [[ARM]] implementation designed by [[ARM Holdings]] (then [[Acorn Computers]]) as a successor to the {{\\|ARM2}}.
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== Overview ==
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The ARM3 builds on the ARM2 with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 can operate at up to 25 MHz with a peak performance of 25 MIPS and a sustainable performance of 12 MIPS.
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== Process Technology ==
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{{see also|1.5 µm process}}
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The ARM3 was implemented on a [[1.5 µm]] double-level metal [[CMOS]] process.
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== Architecture ==
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=== Key changes from {{\\|ARM2}} ===
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* Goal 3x the performance
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==== New instructions ====
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New ARM3 instructions:
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'''Memory:'''
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* <code>SWP</code> - Swap word memory-register, Atomic (uninterruptible)
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== Die ==
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* 12 MHz, 1 W
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* [[1.5 µm]] DLM CMOS
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* 8.72 mm x 9.95 mm
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* 86.764 mm² die size
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* 309,656 transistors
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** 206,454 SRAM
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** 62,973 CAM
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** 40,229 logic
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* QFP-160
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** 119 signal pins
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** 41 power/ground pins
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== All ARM2 Chips ==
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{{empty section}}
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== References ==
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* Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.

Revision as of 17:19, 28 June 2017

Edit Values
ARM3 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerVLSI Technology, Sanyo
Introduction1989
Process1.5 µm
Core Configs1
Pipeline
TypeScalar, Pipelined
Stages3
Decode1-way
Instructions
ISAARMv2a
Succession

ARM3 is the second-generation commercial ARM implementation designed by ARM Holdings (then Acorn Computers) as a successor to the ARM2.

Overview

The ARM3 builds on the ARM2 with higher performance through the introduction of on-die cache but without any major changes to the core itself. The ARM3 can operate at up to 25 MHz with a peak performance of 25 MIPS and a sustainable performance of 12 MIPS.

Process Technology

See also: 1.5 µm process

The ARM3 was implemented on a 1.5 µm double-level metal CMOS process.

Architecture

Key changes from ARM2

  • Goal 3x the performance

New instructions

New ARM3 instructions:

Memory:

  • SWP - Swap word memory-register, Atomic (uninterruptible)

Die

  • 12 MHz, 1 W
  • 1.5 µm DLM CMOS
  • 8.72 mm x 9.95 mm
  • 86.764 mm² die size
  • 309,656 transistors
    • 206,454 SRAM
    • 62,973 CAM
    • 40,229 logic
  • QFP-160
    • 119 signal pins
    • 41 power/ground pins

All ARM2 Chips

New text document.svg This section is empty; you can help add the missing info by editing this page.

References

  • Thomas, A. R. P., et al. "A 2nd Generation 32b RISC Processor with 4KByte Cache." Solid-State Circuits Conference, 1989. ESSCIRC'89. Proceedings of the 15th European. IEEE, 1989.
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Facts about "ARM3 - Microarchitectures - Acorn"
RDF feed
codenameARM3 +
core count1 +
designerARM Holdings +
first launched1989 +
full page nameacorn/microarchitectures/arm3 +
instance ofmicroarchitecture +
instruction set architectureARMv2a +
manufacturerVLSI Technology + and Sanyo +
microarchitecture typeCPU +
nameARM3 +
pipeline stages3 +
process1,500 nm (1.5 μm, 0.0015 mm) +