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Difference between revisions of "fujitsu/sparc64/sparc64 xii"
< fujitsu‎ | sparc64

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'''SPARC64 XII''' is a high-performance {{arch|64}} [[dodeca-core]] [[SPARC]] microprocessor designed by [[Fujitsu]] and introduced in April [[2017]].
 
'''SPARC64 XII''' is a high-performance {{arch|64}} [[dodeca-core]] [[SPARC]] microprocessor designed by [[Fujitsu]] and introduced in April [[2017]].
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== Cache ==
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{{empty section}}
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== Expansions ==
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{{empty section}}
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== Die Shot ==
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* [[20 nn process]]
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[[File:sparc64 xii die shot.png|600px]]
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[[File:sparc64 xii die shot (annotated).png|600px]]

Revision as of 22:22, 12 April 2017

Template:mpu SPARC64 XII is a high-performance 64-bit dodeca-core SPARC microprocessor designed by Fujitsu and introduced in April 2017.

Cache

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Expansions

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Die Shot

sparc64 xii die shot.png


sparc64 xii die shot (annotated).png

Retrieved from "https://en.wikichip.org/w/index.php?title=fujitsu/sparc64/sparc64_xii&oldid=41100"
Facts about "SPARC64 XII - Fujitsu"
RDF feed
base frequency4,250 MHz (4.25 GHz, 4,250,000 kHz) +
core count12 +
designerFujitsu +
familySPARC64 +
first announced2015 +
first launchedApril 4, 2017 +
full page namefujitsu/sparc64/sparc64 xii +
instance ofmicroprocessor +
isaSPARC V9 +
isa familySPARC +
ldateApril 4, 2017 +
main imageFile:sparc64 xii.png +
main image captionSPARC64 XII Chip +
manufacturerTSMC +
market segmentServer +
max cpu count32 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitectureSPARC64 XII +
model numberSPARC64 XII +
nameSPARC64 XII +
process20 nm (0.02 μm, 2.0e-5 mm) +
smp max ways32 +
technologyCMOS +
thread count96 +
word size64 bit (8 octets, 16 nibbles) +