Difference between revisions of "cavium/octeon"

Revision as of 20:08, 8 December 2016

Cavium OCTEON

CN38xx
Developer	Cavium
Manufacturer	TSMC
Type	System on chips
Introduction	September 13, 2004 (announced) June 1, 2005 (launch)
Architecture	MIPS64 R2 network SoCs
ISA	MIPS64
µarch	cnMIPS
Word size	64 bit 8 octets 16 nibbles
Process	130 nm 0.13 μm 1.3e-4 mm
Technology	CMOS
Clock	400 MHz-600 MHz
Package	FCBGA-1521, HSBGA-868
Socket	BGA-1521, BGA-868
Succession
	→
	OCTEON II

OCTEON was a family of 64-bit multi-core MIPS microprocessors designed by Cavium for networking devices.

Overview

The original OCTEON family of network-oriented microprocessors were announced in September of 2004. These chips are based on Cavium's newly announced microarchitecture, cnMIPS, announced the same day. The cnMIPS design is a fully compliant MIPS64 revision 2 implementation. OCTEON chips are found in many enterprise an data center network servers, routers, and switches as well as various high-end residential routers.

Architecture

Main article: cnMIPS µarch

The cnMIPS microarchitecture is a fully-custom design implementing the MIPS64 revision 2 ISA on TSMC's 130 nm process. Due to the specific nature of the applicatons running, an FPU was omitted. Instead, Cavium opted to incorporate a wide array of hardware accelerators for network applications (L3 to L7) including support for compression/decompression algorithms (e.g.GZIP), and security/crypto algorithms (e.g. DES, AES, MD5, and SHA1).

Members

CN3000 Series

CN3000-Series Microprocessors
Model	Price	Launched	Cores	L2$	Power	Freq	Mem Type	Max Mem	ECC
CN3005-300 CP	$ 19.00 € 17.10 £ 15.39 ¥ 1,963.27	1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	2 W 2,000 mW 0.00268 hp 0.002 kW	300 MHz 0.3 GHz 300,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3005-300 SCP	$ 19.00 € 17.10 £ 15.39 ¥ 1,963.27	1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	2 W 2,000 mW 0.00268 hp 0.002 kW	300 MHz 0.3 GHz 300,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3005-400 CP		1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	3 W 3,000 mW 0.00402 hp 0.003 kW	400 MHz 0.4 GHz 400,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3005-400 SCP		1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	3 W 3,000 mW 0.00402 hp 0.003 kW	400 MHz 0.4 GHz 400,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3005-500 CP		1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	4 W 4,000 mW 0.00536 hp 0.004 kW	500 MHz 0.5 GHz 500,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3005-500 SCP		1 May 2006	1	64 KiB 0.0625 MiB 65,536 B 6.103516e-5 GiB	4 W 4,000 mW 0.00536 hp 0.004 kW	500 MHz 0.5 GHz 500,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✘
CN3010-300 CP	$ 39.00 € 35.10 £ 31.59 ¥ 4,029.87	1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	2 W 2,000 mW 0.00268 hp 0.002 kW	300 MHz 0.3 GHz 300,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
CN3010-300 SCP	$ 39.00 € 35.10 £ 31.59 ¥ 4,029.87	1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	2 W 2,000 mW 0.00268 hp 0.002 kW	300 MHz 0.3 GHz 300,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
CN3010-400 CP		1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	3 W 3,000 mW 0.00402 hp 0.003 kW	400 MHz 0.4 GHz 400,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
CN3010-400 SCP		1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	3 W 3,000 mW 0.00402 hp 0.003 kW	400 MHz 0.4 GHz 400,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
CN3010-500 CP		1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	4 W 4,000 mW 0.00536 hp 0.004 kW	500 MHz 0.5 GHz 500,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
CN3010-500 SCP		1 May 2006	1	128 KiB 0.125 MiB 131,072 B 1.220703e-4 GiB	4 W 4,000 mW 0.00536 hp 0.004 kW	500 MHz 0.5 GHz 500,000 kHz	DDR2-533	2,048 MiB 2,097,152 KiB 2,147,483,648 B 2 GiB 0.00195 TiB	✔
Count: 12

Datasheet

@@ Line 50: / Line 50: @@
 -->
 <table class="wikitable sortable">
-<tr><th colspan="9" style="background:#D6D6FF;">CN3000-Series Microprocessors</th></tr>
+<tr><th colspan="10" style="background:#D6D6FF;">CN3000-Series Microprocessors</th></tr>
-<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th></tr>
+<tr><th>Model</th><th>Price</th><th>Launched</th><th>Cores</th><th>L2$</th><th>Power</th><th>Freq</th><th>Mem Type</th><th>Max Mem</th><th>ECC</th></tr>
 {{#ask: [[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3000]]
   |?full page name
@@ Line 63: / Line 63: @@
   |?supported memory type
   |?max memory
+ |?has ecc memory support
   |format=template
-  |template=proc table 2
+  |template=proc table 3
-  |userparam=10
+  |userparam=11:11
   |mainlabel=-
 }}
-{{table count|col=9|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3000]]}}
+{{table count|col=10|ask=[[Category:microprocessor models by cavium]][[microprocessor family::OCTEON]][[microprocessor series::CN3000]]}}
 </table>

designer	Cavium +
first announced	September 13, 2004 +
first launched	June 1, 2005 +
full page name	cavium/octeon +
instance of	system on a chip family +
instruction set architecture	MIPS64 +
main designer	Cavium +
manufacturer	TSMC +
microarchitecture	cnMIPS +
name	Cavium OCTEON +
package	FCBGA-1521 + and HSBGA-868 +
process	130 nm (0.13 μm, 1.3e-4 mm) +
socket	BGA-1521 + and BGA-868 +
technology	CMOS +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas