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{{amd title|K8|arch}} | {{amd title|K8|arch}} | ||
{{microarchitecture | {{microarchitecture | ||
| − | | atype | + | |atype=CPU |
| − | | name | + | |name=K8 |
| − | | designer | + | |designer=AMD |
| − | | manufacturer | + | |manufacturer=AMD |
| − | | introduction | + | |introduction=September 23, 2003 |
| − | + | |process=130 nm | |
| − | | process | + | |process 2=90 nm |
| − | | process 2 | + | |process 3=65 nm |
| − | | process 3 | + | |cores=1 |
| − | | cores | + | |cores 2=2 |
| − | | cores 2 | + | |oooe=Yes |
| + | |renaming=Yes | ||
| + | |decode=3 | ||
|isa=x86-64 | |isa=x86-64 | ||
| − | | | + | |extension=MMX |
| − | | predecessor | + | |extension 2=SSE |
| − | | predecessor link = amd/microarchitectures/k7 | + | |extension 3=SSE2 |
| − | | successor | + | |extension 4=SSE3 (some steppings) |
| − | | successor link | + | |extension 5=3DNow! |
| − | | successor 2 | + | |l1i=64 KiB |
| − | | successor 2 link = amd/microarchitectures/k10 | + | |l1i per=core |
| + | |l1d=64 KiB | ||
| + | |l1d per=core | ||
| + | |predecessor=K7 | ||
| + | |predecessor link=amd/microarchitectures/k7 | ||
| + | |successor=K9 | ||
| + | |successor link=amd/microarchitectures/k9 | ||
| + | |successor 2=K10 | ||
| + | |successor 2 link=amd/microarchitectures/k10 | ||
| + | |succession=Yes | ||
}} | }} | ||
'''K8''' ('''Hammer''') was the [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K7}}. K8 was superseded by {{\\|K10}} in 2007. | '''K8''' ('''Hammer''') was the [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|K7}}. K8 was superseded by {{\\|K10}} in 2007. | ||
Latest revision as of 00:06, 19 June 2023
| Edit Values | |
| K8 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Introduction | September 23, 2003 |
| Process | 130 nm, 90 nm, 65 nm |
| Core Configs | 1, 2 |
| Pipeline | |
| OoOE | Yes |
| Reg Renaming | Yes |
| Decode | 3 |
| Instructions | |
| ISA | x86-64 |
| Extensions | MMX, SSE, SSE2, SSE3 (some steppings), 3DNow! |
| Cache | |
| L1I Cache | 64 KiB/core |
| L1D Cache | 64 KiB/core |
| Succession | |
K8 (Hammer) was the microarchitecture developed by AMD as a successor to K7. K8 was superseded by K10 in 2007.
Contents
Architecture[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Die Shot[edit]
| |
This section is empty; you can help add the missing info by editing this page. |
All K8 Chips[edit]
| K8 Chips | ||||||
|---|---|---|---|---|---|---|
| Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
| Count: 0 | ||||||
See also[edit]
Facts about "K8 - Microarchitectures - AMD"
| codename | K8 + |
| core count | 1 + and 2 + |
| designer | AMD + |
| first launched | September 23, 2003 + |
| full page name | amd/microarchitectures/k8 + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | K8 + |
| process | 130 nm (0.13 μm, 1.3e-4 mm) +, 90 nm (0.09 μm, 9.0e-5 mm) + and 65 nm (0.065 μm, 6.5e-5 mm) + |