From WikiChip
Difference between revisions of "intel/microarchitectures/cooper lake"
m (Reverted edits by 87.98.244.136 (talk) to last revision by David) |
(Correcting Successor and contemporary architectures, fixed cache amounts, added core counts, and removed random designer labeled) |
||
(6 intermediate revisions by 3 users not shown) | |||
Line 5: | Line 5: | ||
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
− | |introduction= | + | |introduction=June 18, 2020 |
− | |process=14 nm | + | |process=14 nm++ |
+ | |cores=28 | ||
+ | |cores 2=24 | ||
+ | |cores 3=20 | ||
+ | |cores 4=18 | ||
+ | |cores 5=16 | ||
+ | |cores 6=8 | ||
|type=Superscalar | |type=Superscalar | ||
|oooe=Yes | |oooe=Yes | ||
Line 51: | Line 57: | ||
|l1d per=core | |l1d per=core | ||
|l1d desc=8-way set associative | |l1d desc=8-way set associative | ||
+ | |l1=64 KiB | ||
+ | |l1 per=core | ||
|l2=1 MiB | |l2=1 MiB | ||
− | |l2 per= | + | |l2 per=Core |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l3=1.375 MiB | |l3=1.375 MiB | ||
Line 62: | Line 70: | ||
|predecessor=Cascade Lake | |predecessor=Cascade Lake | ||
|predecessor link=intel/microarchitectures/cascade lake | |predecessor link=intel/microarchitectures/cascade lake | ||
− | |successor=Ice Lake (Server) | + | |successor=Sapphire Rapids |
− | | | + | |successor link=intel/microarchitectures/sapphire rapids |
− | |contemporary=Coffee Lake | + | |contemporary=Ice Lake (Server) |
− | |contemporary link=intel/microarchitectures/coffee lake | + | |contemporary link=intel/microarchitectures/ice lake (server) |
+ | |contemporary 2=Coffee Lake | ||
+ | |contemporary 2 link=intel/microarchitectures/coffee lake | ||
}} | }} | ||
− | '''Cooper Lake''' ('''CPL''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for | + | '''Cooper Lake''' ('''CPL''' / '''CPX''') is [[Intel]]'s successor to {{\\|Cascade Lake}}, a [[14 nm]] [[microarchitecture]] for the multiprocessing server market only. |
− | + | Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while {{\\|Ice Lake (Server)|Ice Lake}} serves the single and dual-socket segments. | |
+ | For scalable server class processors, Intel branded it as {{intel|Xeon Gold}} and {{intel|Xeon Platinum}}. | ||
== Codenames == | == Codenames == | ||
+ | Single and dual-socket Cooper Lake parts were scrapped before ever making it to market. | ||
{| class="wikitable" | {| class="wikitable" | ||
|- | |- | ||
! Core !! Abbrev !! Target | ! Core !! Abbrev !! Target | ||
− | |- | + | |- style="text-decoration:line-through" |
| {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market | | {{intel|Cooper Lake X|l=core}} || CPL-X || High-end desktops & enthusiasts market | ||
− | |- | + | |- style="text-decoration:line-through" |
| {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations | | {{intel|Cooper Lake W|l=core}} || CPL-W || Enterprise/Business workstations | ||
|- | |- | ||
| {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors | | {{intel|Cooper Lake SP|l=core}} || CPL-SP || Server Scalable Processors | ||
− | |- | + | |- style="text-decoration:line-through" |
| {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors | | {{intel|Cooper Lake AP|l=core}} || CPL-AP || Server Advanced Processors | ||
|} | |} | ||
Line 91: | Line 103: | ||
== Release Dates == | == Release Dates == | ||
[[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]] | [[File:intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png|right|thumb|Cooper Lake and {{\\|Ice Lake}} roadmap.]] | ||
− | Cooper Lake | + | Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020. |
== Process Technology == | == Process Technology == | ||
Line 97: | Line 109: | ||
== Architecture == | == Architecture == | ||
− | |||
=== Key changes from {{\\|Cascade Lake}} === | === Key changes from {{\\|Cascade Lake}} === | ||
+ | * SoC | ||
+ | ** 2x UPI links (6, up from 3) | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
* Memory | * Memory | ||
− | ** Higher | + | ** Higher data rate (3200 MT/s, up from 2933 MT/s) |
− | |||
** Optane DC DIMMs | ** Optane DC DIMMs | ||
*** Apache Pass '''→''' Barlow Pass | *** Apache Pass '''→''' Barlow Pass | ||
+ | |||
* Platform | * Platform | ||
− | ** {{intel|Purley | + | ** {{intel|Purley|l=platform}} '''→''' {{intel|Cedar Island|l=platform}} |
− | + | ||
* Packaging | * Packaging | ||
− | ** 4189-contact flip-chip LGA (up from 3647 contacts) | + | ** Socket-P+ |
+ | *** 4189-contact flip-chip LGA (up from 3647 contacts) | ||
{{expand list}} | {{expand list}} | ||
Latest revision as of 18:40, 26 March 2024
Edit Values | |
Cooper Lake µarch | |
General Info | |
Arch Type | CPU |
Designer | Intel |
Manufacturer | Intel |
Introduction | June 18, 2020 |
Process | 14 nm++ |
Core Configs | 28, 24, 20, 18, 16, 8 |
Pipeline | |
Type | Superscalar |
OoOE | Yes |
Speculative | Yes |
Reg Renaming | Yes |
Stages | 14-19 |
Instructions | |
ISA | x86-64 |
Extensions | MOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, VT-x, VT-d, TXT, TSX, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SGX, MPX, AVX-512 |
Cache | |
L1I Cache | 32 KiB/core 8-way set associative |
L1D Cache | 32 KiB/core 8-way set associative |
L1 Cache | 64 KiB/core |
L2 Cache | 1 MiB/Core 16-way set associative |
L3 Cache | 1.375 MiB/core 11-way set associative |
Cores | |
Core Names | Cooper Lake X, Cooper Lake SP, Cooper Lake AP |
Succession | |
Contemporary | |
Ice Lake (Server) Coffee Lake |
Cooper Lake (CPL / CPX) is Intel's successor to Cascade Lake, a 14 nm microarchitecture for the multiprocessing server market only.
Launched in mid-2020, Cooper Lake covers the 4-way and 8-way multiprocessing segments while Ice Lake serves the single and dual-socket segments.
For scalable server class processors, Intel branded it as Xeon Gold and Xeon Platinum.
Contents
Codenames[edit]
Single and dual-socket Cooper Lake parts were scrapped before ever making it to market.
Core | Abbrev | Target |
---|---|---|
Cooper Lake X | CPL-X | High-end desktops & enthusiasts market |
Cooper Lake W | CPL-W | Enterprise/Business workstations |
Cooper Lake SP | CPL-SP | Server Scalable Processors |
Cooper Lake AP | CPL-AP | Server Advanced Processors |
Brands[edit]
![]() |
This section is empty; you can help add the missing info by editing this page. |
Release Dates[edit]
![](/w/images/thumb/9/93/intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png/300px-intel-2019-investor-meeting-ice-lake-server-cooper-roadmap.png)
Cooper Lake and Ice Lake roadmap.
Cooper was first publicly disclosed in early 2019. Cooper Lake launched on June 18, 2020.
Process Technology[edit]
Cooper Lake is fabricated on Intel's 3rd generation enhanced 14nm++ process.
Architecture[edit]
Key changes from Cascade Lake[edit]
- SoC
- 2x UPI links (6, up from 3)
- Memory
- Higher data rate (3200 MT/s, up from 2933 MT/s)
- Optane DC DIMMs
- Apache Pass → Barlow Pass
- Platform
- Packaging
- Socket-P+
- 4189-contact flip-chip LGA (up from 3647 contacts)
- Socket-P+
This list is incomplete; you can help by expanding it.
New instructions[edit]
Cooper Lake introduced a number of new instructions:
- BFLOAT16 - A new data type for acceleration of AI workloads.
- AVX512 BF16 - AVX-512 Brain Float 16 extension
See also[edit]
Facts about "Cooper Lake - Microarchitectures - Intel"
codename | Cooper Lake + |
core count | 28 +, 24 +, 20 +, 18 +, 16 + and 8 + |
designer | Intel + |
first launched | June 18, 2020 + |
full page name | intel/microarchitectures/cooper lake + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | Intel + |
microarchitecture type | CPU + |
name | Cooper Lake + |
pipeline stages (max) | 19 + |
pipeline stages (min) | 14 + |