Difference between revisions of "intel/xeon gold/5218r"

	Edit Values
	Xeon Gold 5218R
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	5218R
Market	Server
Introduction	February 24, 2020 (announced); February 24, 2020 (launched)
Release Price	$1,273.00 (tray); $1,280.00 (box)
Shop	Amazon
	General Specs
Family	Xeon Gold
Series	6200
Locked	Yes
Frequency	2,100 MHz
Turbo Frequency	4,000 MHz (1 core)
Bus type	DMI 3.0
Bus rate	4 × 8 GT/s
Clock multiplier	21
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake R
Core Family	6
Core Model	85
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	20
Threads	40
Max Memory	1 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	10.4 GT/s
	Electrical
TDP	125 W
Tcase	0 °C – 87 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Gold 5218

Latest revision as of 01:34, 28 February 2020

Xeon Gold 5218R is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2020. The Gold 5218R is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 2-way multiprocessing, sports a single AVX-512 FMA unit as well as two Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 125 W and features a turbo boost frequency of up to 4.0 GHz.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

1.25 MiB

1,280 KiB
1,310,720 B

L1I$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative
L1D$	640 KiB 655,360 B 0.625 MiB	20x32 KiB	8-way set associative	write-back

L2$

20 MiB

20,480 KiB
20,971,520 B
0.0195 GiB

		20x1 MiB	16-way set associative	write-back

L3$

27.5 MiB

28,160 KiB
28,835,840 B
0.0269 GiB

		20x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2666
Supports ECC	Yes
Max Mem	1 TiB
Controllers	2
Channels	6
Max Bandwidth	119.21 GiB/s 122,071.04 MiB/s 128.001 GB/s 128,000.763 MB/s 0.116 TiB/s 0.128 TB/s
Bandwidth	Single 19.87 GiB/s Double 39.74 GiB/s Quad 79.47 GiB/s Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: 1x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit (1 Unit)
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control
DL Boost	Deep Learning Boost

@@ Line 45: / Line 45: @@
 |predecessor link=intel/xeon_gold/5218
 }}
-'''Xeon Gold 5218R''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 5218R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
+'''Xeon Gold 5218R''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2020]]. The Gold 5218R is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 2-way multiprocessing, sports a single {{x86|AVX-512}} [[FMA]] unit as well as two {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.1 GHz with a TDP of 125 W and features a {{intel|turbo boost}} frequency of up to 4.0 GHz.
 == Cache ==
@@ Line 131: / Line 131: @@
 |avx5124vnniw=No
 |avx512vpopcntdq=No
-|avx512units=2
+|avx512units=1
 |avx512gfni=No
 |avx512vaes=No

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Gold 5218R - Intel#pcie +
base frequency	2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links	4 +
bus rate	8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus type	DMI 3.0 +
chipset	Lewisburg +
clock multiplier	21 +
core count	20 +
core family	6 +
core model	85 +
core name	Cascade Lake R +
designer	Intel +
family	Xeon Gold +
first announced	February 24, 2020 +
first launched	February 24, 2020 +
full page name	intel/xeon gold/5218r +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	1,280 KiB (1,310,720 B, 1.25 MiB) +
l1d$ description	8-way set associative +
l1d$ size	640 KiB (655,360 B, 0.625 MiB) +
l1i$ description	8-way set associative +
l1i$ size	640 KiB (655,360 B, 0.625 MiB) +
l2$ description	16-way set associative +
l2$ size	20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) +
l3$ description	11-way set associative +
l3$ size	27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) +
ldate	February 24, 2020 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	360.15 K (87 °C, 188.6 °F, 648.27 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	5218R +
name	Xeon Gold 5218R +
number of avx-512 execution units	1 +
package	FCLGA-3647 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) + and $ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) +
release price (box)	$ 1,280.00 (€ 1,152.00, £ 1,036.80, ¥ 132,262.40) +
release price (tray)	$ 1,273.00 (€ 1,145.70, £ 1,031.13, ¥ 131,539.09) +
series	6200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	10.4 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2666 +
tdp	125 W (125,000 mW, 0.168 hp, 0.125 kW) +
technology	CMOS +
thread count	40 +
turbo frequency (1 core)	4,000 MHz (4 GHz, 4,000,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas