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Difference between revisions of "nervana/nnp/nnp-i 1100"
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|process=10 nm
 
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|transistors=8,500,000,000
 
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'''NNP-I 1100''' is an inference [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on [[Intel's 10 nm process]] based on the {{intel|Spring Hill|l=arch}} microarchitecture, the NNP-I 1100 has 12 {{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} for a peak performance of 50 [[TOPS]] at a TDP of 12 W. This chip comes in an [[M.2]] [[accelerator card]] form factor.
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'''NNP-I 1100''' is an [[inference]] [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on [[Intel's 10 nm process]] based on the {{intel|Spring Hill|l=arch}} microarchitecture, the NNP-I 1100 has 12 {{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} for a peak performance of 50 [[TOPS]] at a TDP of 12 W. This chip comes in an [[M.2]] [[accelerator card]] form factor.
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[[File:spring hill m.2 (front).png|right|thumb|Nervana NNP-I 1100 M.2 [[accelerator card]].]]
  
 
== Peak Performance ==
 
== Peak Performance ==

Latest revision as of 11:48, 1 February 2020

Edit Values
NNP-I 1100
spring hill package (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberNNP-I 1100
MarketServer, Edge
IntroductionNovember 12, 2019 (announced)
November 12, 2019 (launched)
ShopAmazon
General Specs
FamilyNNP
SeriesNNP-I
Microarchitecture
MicroarchitectureSpring Hill, Sunny Cove
Process10 nm
Transistors8,500,000,000
TechnologyCMOS
Die239 mm²
Cores12
Electrical
TDP12 W
Packaging
spring hill package (back).png

NNP-I 1100 is an inference neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on Intel's 10 nm process based on the Spring Hill microarchitecture, the NNP-I 1100 has 12 ICEs for a peak performance of 50 TOPS at a TDP of 12 W. This chip comes in an M.2 accelerator card form factor.

Nervana NNP-I 1100 M.2 accelerator card.

Peak Performance[edit]

The NNP-I 1100 has a peak performance of 50 TOPS
50,000,000,000,000 OPS
50,000,000,000 KOPS
50,000,000 MOPS
50,000 GOPS
0.05 POPS
(Int8).

Cache[edit]

Main article: Spring Hill § Cache
  • 3 MiB of tightly-coupled scratchpad memory
    • 12 x 256 KiB/core
  • 48 MiB Deep SRAM
    • 4 MiB/ICE
  • 24 MiB LLC
    • 3 MiB/slice

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-4200
Supports ECCYes
Max Mem32 GiB
Controllers4
Width16
Max Bandwidth67.2 GB/s
62.585 GiB/s
64,086.914 MiB/s
67,200 MB/s
0.0611 TiB/s
0.0672 TB/s

Die[edit]

Main article: Spring Hill § Die
  • 8,500,000,000 transistors
  • 239 mm² die size

Product Brief[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=nervana/nnp/nnp-i_1100&oldid=95731"
Facts about "NNP-I 1100 - Intel Nervana"
RDF feed
back imageFile:spring hill package (back).png +
core count12 +
designerIntel +
die area239 mm² (0.37 in², 2.39 cm², 239,000,000 µm²) +
familyNNP +
first announcedNovember 12, 2019 +
first launchedNovember 12, 2019 +
full page namenervana/nnp/nnp-i 1100 +
has ecc memory supporttrue +
instance ofmicroprocessor +
ldateNovember 12, 2019 +
main imageFile:spring hill package (front).png +
manufacturerIntel +
market segmentServer + and Edge +
max memory bandwidth62.585 GiB/s (64,086.914 MiB/s, 67.2 GB/s, 67,200 MB/s, 0.0611 TiB/s, 0.0672 TB/s) +
microarchitectureSpring Hill + and Sunny Cove +
model numberNNP-I 1100 +
nameNNP-I 1100 +
peak integer ops (8-bit)50,000,000,000,000 OPS (50,000,000,000 KOPS, 50,000,000 MOPS, 50,000 GOPS, 50 TOPS, 0.05 POPS, 5.0e-5 EOPS, 5.0e-8 ZOPS) +
process10 nm (0.01 μm, 1.0e-5 mm) +
seriesNNP-I +
supported memory typeLPDDR4X-4200 +
tdp12 W (12,000 mW, 0.0161 hp, 0.012 kW) +
technologyCMOS +
transistor count8,500,000,000 +