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Difference between revisions of "nervana/nnp/nnp-i 1300"
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|series=NNP-I | |series=NNP-I | ||
|microarch=Spring Hill | |microarch=Spring Hill | ||
+ | |microarch 2=Sunny Cove | ||
|process=10 nm | |process=10 nm | ||
|transistors=8,500,000,000 | |transistors=8,500,000,000 | ||
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|tdp=75 W | |tdp=75 W | ||
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− | '''NNP-I 1300''' is an inference [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on [[Intel's 10 nm process]] based on the {{intel|Spring Hill|l=arch}} microarchitecture, the NNP-I 1300 comes in a PCIe Gen 3.0 [[accelerator card]] form factor with two NPU chips, each with all 24 {{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} enabled for a peak performance of 170 [[TOPS]] at a TDP of 75 W. | + | '''NNP-I 1300''' is an [[inference]] [[neural processor]] designed by [[Intel Nervana]] and introduced in late 2019. Fabricated on [[Intel's 10 nm process]] based on the {{intel|Spring Hill|l=arch}} microarchitecture, the NNP-I 1300 comes in a PCIe Gen 3.0 [[accelerator card]] form factor with two NPU chips, each with all 24 {{intel|Spring Hill#Inference Compute Engine (ICE)|ICEs|l=arch}} enabled for a peak performance of 170 [[TOPS]] at a TDP of 75 W. |
+ | |||
+ | == Peak Performance == | ||
+ | The NNP-I 1300 has a peak performance of [[peak integer ops (8-bit)::170 TOPS]] ([[Int8]]). | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/spring_hill#Memory_Hierarchy|l1=Spring Hill § Cache}} | ||
+ | * 3 MiB of tightly-coupled scratchpad memory | ||
+ | ** 12 x 256 KiB/core | ||
+ | * 48 MiB Deep SRAM | ||
+ | ** 4 MiB/ICE | ||
+ | * 24 MiB [[last level cache|LLC]] | ||
+ | ** 3 MiB/slice | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=LPDDR4X-4200 | ||
+ | |ecc=Yes | ||
+ | |max mem=32 GiB | ||
+ | |controllers=4 | ||
+ | |width=16 | ||
+ | |max bandwidth=67.2 GB/s | ||
+ | }} | ||
+ | |||
+ | == Die == | ||
+ | {{main|intel/microarchitectures/spring_hill#Die|l1=Spring Hill § Die}} | ||
+ | * 8,500,000,000 transistors | ||
+ | * 239 mm² die size | ||
+ | |||
+ | == Product Brief == | ||
+ | * [[:File:16433-1 NNP-announce NNP-I brief v5.1.pdf|Intel NNP-I Product Brief]] |
Latest revision as of 12:49, 1 February 2020
Edit Values | |
NNP-I 1300 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | NNP-I 1300 |
Market | Server, Edge |
Introduction | November 12, 2019 (announced) November 12, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | NNP |
Series | NNP-I |
Microarchitecture | |
Microarchitecture | Spring Hill, Sunny Cove |
Process | 10 nm |
Transistors | 8,500,000,000 |
Technology | CMOS |
Die | 239 mm² |
Cores | 24 |
Electrical | |
TDP | 75 W |
Packaging | |
![]() |
NNP-I 1300 is an inference neural processor designed by Intel Nervana and introduced in late 2019. Fabricated on Intel's 10 nm process based on the Spring Hill microarchitecture, the NNP-I 1300 comes in a PCIe Gen 3.0 accelerator card form factor with two NPU chips, each with all 24 ICEs enabled for a peak performance of 170 TOPS at a TDP of 75 W.
Peak Performance[edit]
The NNP-I 1300 has a peak performance of 170 TOPS170,000,000,000,000 OPS
170,000,000,000 KOPS
170,000,000 MOPS
170,000 GOPS
0.17 POPS
(Int8).
170,000,000,000 KOPS
170,000,000 MOPS
170,000 GOPS
0.17 POPS
Cache[edit]
- Main article: Spring Hill § Cache
- 3 MiB of tightly-coupled scratchpad memory
- 12 x 256 KiB/core
- 48 MiB Deep SRAM
- 4 MiB/ICE
- 24 MiB LLC
- 3 MiB/slice
Memory controller[edit]
![]() |
Integrated Memory Controller
|
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|
Die[edit]
- Main article: Spring Hill § Die
- 8,500,000,000 transistors
- 239 mm² die size
Product Brief[edit]
Facts about "NNP-I 1300 - Intel Nervana"
full page name | nervana/nnp/nnp-i 1300 + |
instance of | microprocessor + |
ldate | 1900 + |