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{{amd title|EPYC 7302P}}
 
{{amd title|EPYC 7302P}}
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{{chip}}
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{{chip
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'''EPYC 7302P''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7302P has a TDP of 155 W with a base frequency of 2.8 GHz and a {{amd|precision boost|boost}} frequency of up to 3.3 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
+
|name=EPYC 7302P
 +
|no image=Yes
 +
|designer=AMD
 +
|manufacturer=TSMC
 +
|manufacturer 2=GlobalFoundries
 +
|model number=7302P
 +
|part number=100-000000049
 +
|part number 2=100-100000049WOF
 +
|market=Server
 +
|first announced=August 7, 2019
 +
|first launched=August 7, 2019
 +
|release price=$825.00
 +
|family=EPYC
 +
|series=7002
 +
|locked=Yes
 +
|frequency=3,000 MHz
 +
|turbo frequency=3,300 MHz
 +
|clock multiplier=30
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Zen 2
 +
|core name=Rome
 +
|core family=23
 +
|core model=49
 +
|core stepping=B0
 +
|process=7 nm
 +
|process 2=14 nm
 +
|technology=CMOS
 +
|mcp=Yes
 +
|die count=5
 +
|word size=64 bit
 +
|core count=16
 +
|thread count=32
 +
|max cpus=1
 +
|max memory=4 TiB
 +
|tdp=155 W
 +
|package name 1=amd,socket_sp3
 +
}}
 +
'''EPYC 7302P''' is a {{arch|64}} [[hexadeca-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7302P has a TDP of 155 W with a base frequency of 3.0 GHz and a {{amd|precision boost|boost}} frequency of up to 3.3 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
 +
 
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}}
 +
{{cache size
 +
|l1 cache=1 MiB
 +
|l1i cache=512 KiB
 +
|l1i break=16x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=512 KiB
 +
|l1d break=16x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=16x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=128 MiB
 +
|l3 break=8x16 MiB
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-3200
 +
|ecc=Yes
 +
|max mem=4 TiB
 +
|controllers=8
 +
|channels=8
 +
|max bandwidth=190.7 GiB/s
 +
|bandwidth schan=23.84 GiB/s
 +
|bandwidth dchan=47.68 GiB/s
 +
|bandwidth qchan=95.37 GiB/s
 +
|bandwidth hchan=143.1 GiB/s
 +
|bandwidth ochan=190.7 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=4.0
 +
|pcie lanes=128
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|sse_gfni=No
 +
|avx=Yes
 +
|avx_gfni=No
 +
|avx2=Yes
 +
|avx512f=No
 +
|avx512cd=No
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=No
 +
|avx512dq=No
 +
|avx512vl=No
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=No
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512gfni=No
 +
|avx512vaes=No
 +
|avx512vbmi2=No
 +
|avx512bitalg=No
 +
|avx512vpclmulqdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=Yes
 +
|amdtsme=Yes
 +
|amdsev=Yes
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=Yes
 +
|amdpbod=No
 +
}}
 +
 
 +
== References ==
 +
* [https://www.amd.com/en/products/cpu/amd-epyc-7302p "AMD EPYC™ 7302P"]. <i>AMD.com</i>. Retrieved October 2020.
 +
* [https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020

Latest revision as of 18:29, 9 January 2021

Edit Values
EPYC 7302P
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
Model Number7302P
Part Number100-000000049,
100-100000049WOF
MarketServer
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
Release Price$825.00
ShopAmazon
General Specs
FamilyEPYC
Series7002
LockedYes
Frequency3,000 MHz
Turbo Frequency3,300 MHz
Clock multiplier30
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Core Model49
Core SteppingB0
Process7 nm, 14 nm
TechnologyCMOS
MCPYes (5 dies)
Word Size64 bit
Cores16
Threads32
Max Memory4 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP155 W
Packaging
PackageSP3, FCLGA-4094 (FC-OLGA)
Dimension75.4 mm × 58.5 mm × 6.26 mm
Pitch0.87 mm × 1 mm
Contacts4094
SocketSP3, LGA-4094

EPYC 7302P is a 64-bit hexadeca-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7302P has a TDP of 155 W with a base frequency of 3.0 GHz and a boost frequency of up to 3.3 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.

Cache[edit]

Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1 MiB
1,024 KiB
1,048,576 B
L1I$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16x512 KiB8-way set associativewrite-back
L3$128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
  8x16 MiB  

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem4 TiB
Controllers8
Channels8
Max Bandwidth190.7 GiB/s
195,276.8 MiB/s
204.763 GB/s
204,762.566 MB/s
0.186 TiB/s
0.205 TB/s
Bandwidth
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Hexa 143.1 GiB/s
Octa 190.7 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 128
Configuration: x16, x8


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Boost 2Precision Boost 2

References[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/epyc/7302p&oldid=98373"
Facts about "EPYC 7302P - AMD"
RDF feed
base frequency2,800 MHz (2.8 GHz, 2,800,000 kHz) +
clock multiplier28 +
core count16 +
core family23 +
core nameRome +
designerAMD +
die count5 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7302p +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count1 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
microarchitectureZen 2 +
model number7302P +
nameEPYC 7302P +
packageSP3 + and FCLGA-4094 +
part number100-000000049 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
series7002 +
smp max ways1 +
socketSP3 + and LGA-4094 +
tdp155 W (155,000 mW, 0.208 hp, 0.155 kW) +
technologyCMOS +
thread count32 +
turbo frequency3,300 MHz (3.3 GHz, 3,300,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +