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{{amd title|EPYC 7272}} | {{amd title|EPYC 7272}} | ||
− | {{chip}} | + | {{chip |
− | '''EPYC 7272''' is a {{arch|64}} [[dodeca-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates | + | |name=EPYC 7272 |
+ | |no image=Yes | ||
+ | |designer=AMD | ||
+ | |manufacturer=TSMC | ||
+ | |manufacturer 2=GlobalFoundries | ||
+ | |model number=7272 | ||
+ | |part number=100-000000079 | ||
+ | |part number 2=100-100000079WOF | ||
+ | |market=Server | ||
+ | |first announced=August 7, 2019 | ||
+ | |first launched=August 7, 2019 | ||
+ | |release price (tray)=$625.00 | ||
+ | |family=EPYC | ||
+ | |series=7002 | ||
+ | |locked=Yes | ||
+ | |frequency=2,900 MHz | ||
+ | |turbo frequency=3,200 MHz | ||
+ | |clock multiplier=29 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Zen 2 | ||
+ | |core name=Rome | ||
+ | |core family=23 | ||
+ | |core model=49 | ||
+ | |core stepping=B0 | ||
+ | |process=7 nm | ||
+ | |process 2=14 nm | ||
+ | |technology=CMOS | ||
+ | |mcp=Yes | ||
+ | |die count=3 | ||
+ | |word size=64 bit | ||
+ | |core count=12 | ||
+ | |thread count=24 | ||
+ | |max cpus=2 | ||
+ | |max memory=4 TiB | ||
+ | |tdp=120 W | ||
+ | |package name 1=amd,socket_sp3 | ||
+ | }} | ||
+ | '''EPYC 7272''' is a {{arch|64}} [[dodeca-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates two compute dies fabricated on a [[TSMC]] [[7 nm process]] and an I/O die fabricated on a [[GlobalFoundries]] [[14 nm process]]. The 7272 has a TDP of 120 W with a base frequency of 2.9 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports up to two-way [[symmetric multiprocessing|SMP]] and up to 4 TiB of memory per socket. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|amd/microarchitectures/zen 2#Memory_Hierarchy|l1=Zen 2 § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=768 KiB | ||
+ | |l1i cache=384 KiB | ||
+ | |l1i break=12x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=384 KiB | ||
+ | |l1d break=12x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=6 MiB | ||
+ | |l2 break=12x512 KiB | ||
+ | |l2 desc=8-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=64 MiB | ||
+ | |l3 break=4x16 MiB | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | This model supports up to 8 channels of up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7272 "AMD EPYC™ 7272"]. <i>AMD.com</i>. Retrieved October 2020.</ref><ref name="datasheet">[https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020</ref> with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the [[amd/infinity_fabric|IFOP]] links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK<ref name="isscc2020j-chiplet">Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:[https://doi.org/10.1109/ISSCC19947.2020.9063103 10.1109/ISSCC19947.2020.9063103]</ref>). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).<ref name="datasheet"/> | ||
+ | |||
+ | {{memory controller | ||
+ | |type=DDR4-3200 | ||
+ | |ecc=Yes | ||
+ | |max mem=4 TiB | ||
+ | |controllers=8 | ||
+ | |channels=8 | ||
+ | |max bandwidth=190.7 GiB/s | ||
+ | |bandwidth schan=23.84 GiB/s | ||
+ | |bandwidth dchan=47.68 GiB/s | ||
+ | |bandwidth qchan=95.37 GiB/s | ||
+ | |bandwidth hchan=143.1 GiB/s | ||
+ | |bandwidth ochan=190.7 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=4.0 | ||
+ | |pcie lanes=128 | ||
+ | |pcie config=x16 | ||
+ | |pcie config 2=x8 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |sse_gfni=No | ||
+ | |avx=Yes | ||
+ | |avx_gfni=No | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |avx512gfni=No | ||
+ | |avx512vaes=No | ||
+ | |avx512vbmi2=No | ||
+ | |avx512bitalg=No | ||
+ | |avx512vpclmulqdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=No | ||
+ | |tbmt3=No | ||
+ | |tvb=No | ||
+ | |bpt=No | ||
+ | |eist=No | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=No | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=No | ||
+ | |vtd=No | ||
+ | |ept=No | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=Yes | ||
+ | |amdtsme=Yes | ||
+ | |amdsev=Yes | ||
+ | |rvi=No | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=Yes | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == References == | ||
+ | <references/> |
Latest revision as of 19:35, 9 January 2021
Edit Values | |
EPYC 7272 | |
General Info | |
Designer | AMD |
Manufacturer | TSMC, GlobalFoundries |
Model Number | 7272 |
Part Number | 100-000000079, 100-100000079WOF |
Market | Server |
Introduction | August 7, 2019 (announced) August 7, 2019 (launched) |
Release Price | $625.00 (tray) |
Shop | Amazon |
General Specs | |
Family | EPYC |
Series | 7002 |
Locked | Yes |
Frequency | 2,900 MHz |
Turbo Frequency | 3,200 MHz |
Clock multiplier | 29 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Zen 2 |
Core Name | Rome |
Core Family | 23 |
Core Model | 49 |
Core Stepping | B0 |
Process | 7 nm, 14 nm |
Technology | CMOS |
MCP | Yes (3 dies) |
Word Size | 64 bit |
Cores | 12 |
Threads | 24 |
Max Memory | 4 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 120 W |
Packaging | |
Package | SP3, FCLGA-4094 (FC-OLGA) |
Dimension | 75.4 mm × 58.5 mm × 6.26 mm |
Pitch | 0.87 mm × 1 mm |
Contacts | 4094 |
Socket | SP3, LGA-4094 |
EPYC 7272 is a 64-bit dodeca-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates two compute dies fabricated on a TSMC 7 nm process and an I/O die fabricated on a GlobalFoundries 14 nm process. The 7272 has a TDP of 120 W with a base frequency of 2.9 GHz and a boost frequency of up to 3.2 GHz. This processor supports up to two-way SMP and up to 4 TiB of memory per socket.
Cache[edit]
- Main article: Zen 2 § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
This model supports up to 8 channels of up to DDR4-3200 memory[1][2] with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the IFOP links between the I/O die and its only two compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK[3]). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).[2]
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Integrated Memory Controller
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Expansions[edit]
![]() |
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
References[edit]
- ↑ "AMD EPYC™ 7272". AMD.com. Retrieved October 2020.
- ↑ 2.0 2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
- ↑ Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103
full page name | amd/epyc/7272 + |
instance of | microprocessor + |
ldate | 1900 + |