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(i5-1030G4)
 
(corructing iGPU from intel datasheet https://www.intel.com/content/www/us/en/products/docs/processors/core/10th-gen-core-families-datasheet-vol-1.html)
 
(8 intermediate revisions by one other user not shown)
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{{intel title|Core i5-1030G4}}
 
{{intel title|Core i5-1030G4}}
−
{{chips}}
+
{{chip
 +
|name=Core i5-1030G4
 +
|image=ice lake y (front).png
 +
|back image=ice lake y (back).png
 +
|caption=package, front
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=i5-1030G4
 +
|market=Mobile
 +
|first announced=August 1, 2019
 +
|first launched=August 1, 2019
 +
|family=Core i5
 +
|series=i5-10000
 +
|locked=Yes
 +
|frequency=700 MHz
 +
|turbo frequency1=3,500 MHz
 +
|turbo frequency4=3,200 MHz
 +
|bus type=OPI
 +
|bus links=4
 +
|bus rate=4 GT/s
 +
|clock multiplier=7
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Ice Lake (Client)
 +
|platform=Ice Lake
 +
|core name=Ice Lake Y
 +
|core family=6
 +
|process=10 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=4
 +
|thread count=8
 +
|max cpus=1
 +
|max memory=32 GiB
 +
|tdp=9 W
 +
|ctdp up=12 W
 +
|ctdp up frequency=1,000 MHz
 +
|tjunc min=0 °C
 +
|tjunc max=100 °C
 +
|package name 1=intel,fcbga_1377
 +
}}
 +
'''Core i5-1030G4''' is a {{arch|64}} [[quad-core]] high-end performance ultra-low power [[x86]] mobile microprocessor introduced by [[Intel]] in mid-[[2019]]. This chip, which is based on the {{intel|Ice Lake|l=arch}} microarchitecture, is fabricated on Intel's [[10 nm process]]. The i5-1030G4 operates at 700 MHz with a TDP of 9 W supporting a {{intel|Turbo Boost}} frequency of up to 3.5 GHz. The processor supports up to 32 GiB of quad-channel LPDDR4X-3733 memory and incorporates Intel's Iris Plus Graphics [[IGP]] operating at 300 MHz with a burst frequency of 1.05 GHz.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/ice lake (client)#Memory_Hierarchy|l1=Ice Lake § Cache}}
 +
{{cache size
 +
|l1 cache=320 KiB
 +
|l1i cache=128 KiB
 +
|l1i break=4x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=192 KiB
 +
|l1d break=4x48 KiB
 +
|l1d desc=12-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=2 MiB
 +
|l2 break=4x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=6 MiB
 +
|l3 break=4x1.5 MiB
 +
|l3 desc=12-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=LPDDR4X-3733
 +
|type 2=DDR4-3200
 +
|ecc=No
 +
|max mem=32 GiB
 +
|controllers=1
 +
|channels=4
 +
|width=32 bit
 +
|max bandwidth=55.63 GiB/s
 +
|bandwidth schan=13.91 GiB/s
 +
|bandwidth dchan=27.82 GiB/s
 +
|bandwidth qchan=55.63 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=USB
 +
|usb revision=USB 3.2 Gen 2x1
 +
|usb ports=4
 +
|usb rate=10 Gb/s
 +
}}
 +
}}
 +
 
 +
== Graphics ==
 +
{{integrated graphics
 +
| gpu                = Iris Plus Graphics
 +
| device id          = 0x8A5C
 +
| designer            = Intel
 +
| execution units    = 48
 +
| max displays        = 3
 +
| max memory          = 32 GiB
 +
| frequency          = 300 MHz
 +
| max frequency      = 1,050 MHz
 +
 
 +
| output crt          =
 +
| output sdvo        =
 +
| output dsi          =
 +
| output edp          = Yes
 +
| output dp          = Yes
 +
| output hdmi        = Yes
 +
| output vga          =
 +
| output dvi          = Yes
 +
 
 +
| directx ver        = 12
 +
| opengl ver        = 4.5
 +
| opencl ver        = 2.0
 +
| hdmi ver          = 2.0b
 +
| dp ver            = 1.4a
 +
| edp ver            = 1.4b
 +
| max res hdmi      = 4Kx2K
 +
| max res hdmi freq  = 60 Hz
 +
| max res dp        = 5120x3200
 +
| max res dp freq    = 60 Hz
 +
| max res edp        = 5120x3200
 +
| max res edp freq  = 60 Hz
 +
| max res vga        =
 +
| max res vga freq  =
 +
 
 +
| features            = Yes
 +
| intel quick sync    = Yes
 +
| intel intru 3d      =
 +
| intel insider        =
 +
| intel widi          =
 +
| intel fdi            =
 +
| intel clear video    =
 +
| intel clear video hd =
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|sse_gfni=Yes
 +
|avx=Yes
 +
|avx_gfni=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=Yes
 +
|avx512gfni=Yes
 +
|avx512vaes=Yes
 +
|avx512vbmi2=Yes
 +
|avx512bitalg=Yes
 +
|avx512vpclmulqdq=Yes
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|tvb=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=Yes
 +
|fastmem=No
 +
|ivmd=No
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=Yes
 +
|vpro=No
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=Yes
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 
 +
== Die ==
 +
{{main|intel/microarchitectures/ice_lake_(client)#SoC|l1=Ice Lake SoC Die}}
 +
 
 +
:[[File:ice lake die (quad core) (annotated).png|500px|link=intel/microarchitectures/ice_lake_(client)#SoC]]
 +
 
 +
:[[File:ice lake die (quad core).png|500px|link=intel/microarchitectures/ice_lake_(client)#SoC]]

Latest revision as of 10:34, 18 March 2020

Edit Values
Core i5-1030G4
ice lake y (front).png
package, front
General Info
DesignerIntel
ManufacturerIntel
Model Numberi5-1030G4
MarketMobile
IntroductionAugust 1, 2019 (announced)
August 1, 2019 (launched)
ShopAmazon
General Specs
FamilyCore i5
Seriesi5-10000
LockedYes
Frequency700 MHz
Turbo Frequency3,500 MHz (1 core),
3,200 MHz (4 cores)
Bus typeOPI
Bus rate4 × 4 GT/s
Clock multiplier7
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureIce Lake (Client)
PlatformIce Lake
Core NameIce Lake Y
Core Family6
Process10 nm
TechnologyCMOS
Word Size64 bit
Cores4
Threads8
Max Memory32 GiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP9 W
cTDP up12 W
cTDP up frequency1,000 MHz
Tjunction0 °C – 100 °C
Packaging
PackageFCBGA-1377 (BGA)
Dimension26.5 mm × 18.5 mm × 1.0 mm
Pitch0.43 mm
Contacts1377
SocketType 3
ice lake y (back).png

Core i5-1030G4 is a 64-bit quad-core high-end performance ultra-low power x86 mobile microprocessor introduced by Intel in mid-2019. This chip, which is based on the Ice Lake microarchitecture, is fabricated on Intel's 10 nm process. The i5-1030G4 operates at 700 MHz with a TDP of 9 W supporting a Turbo Boost frequency of up to 3.5 GHz. The processor supports up to 32 GiB of quad-channel LPDDR4X-3733 memory and incorporates Intel's Iris Plus Graphics IGP operating at 300 MHz with a burst frequency of 1.05 GHz.

Cache[edit]

Main article: Ice Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$320 KiB
327,680 B
0.313 MiB
L1I$128 KiB
131,072 B
0.125 MiB
4x32 KiB8-way set associative 
L1D$192 KiB
196,608 B
0.188 MiB
4x48 KiB12-way set associativewrite-back
L2$2 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
  4x512 KiB8-way set associativewrite-back
L3$6 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
  4x1.5 MiB12-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeLPDDR4X-3733, DDR4-3200
Supports ECCNo
Max Mem32 GiB
Controllers1
Channels4
Width32 bit
Max Bandwidth55.63 GiB/s
56,965.12 MiB/s
59.732 GB/s
59,732.258 MB/s
0.0543 TiB/s
0.0597 TB/s
Bandwidth
Single 13.91 GiB/s
Double 27.82 GiB/s
Quad 55.63 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
USBRevision: USB 3.2 Gen 2x1
Max Ports: 4
Rate: 10 Gb/s


Graphics[edit]

[Edit/Modify IGP Info]

screen icon.svg
Integrated Graphics Information
GPUIris Plus Graphics
DesignerIntelDevice ID0x8A5C
Execution Units48Max Displays3
Max Memory32 GiB
32,768 MiB
33,554,432 KiB
34,359,738,368 B
Frequency300 MHz
0.3 GHz
300,000 KHz
Burst Frequency1,050 MHz
1.05 GHz
1,050,000 KHz
OutputDP, eDP, HDMI, DVI
Max Resolution
HDMI4Kx2K @60 Hz
DP5120x3200 @60 Hz
eDP5120x3200 @60 Hz
Standards
DirectX12
OpenGL4.5
OpenCL2.0
DP1.4a
eDP1.4b
HDMI2.0b
Additional Features
Intel Quick Sync Video

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
GFNISSE Galois Field New Instructions
AVXAdvanced Vector Extensions
AVX+GFNIAVX Galois Field New Instructions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
AVX512_VPOPCNTDQAVX-512 Vector Population Count Doubleword and Quadword
AVX512F+GFNIAVX-512 Galois Field New Instructions
AVX512F+VAESAVX-512 Vector AES Instructions
AVX512_VBMI2AVX-512 Vector Bit Manipulation Instructions 2
AVX512_BITALGAVX-512 Bit Algorithms
AVX512F+VPCLMULQDQVector Carry-Less Multiplication of Quadwords
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
MPXMemory Protection Extensions
SGXSoftware Guard Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
Flex MemoryFlex Memory Access

Die[edit]

Main article: Ice Lake SoC Die


ice lake die (quad core) (annotated).png
ice lake die (quad core).png
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