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Difference between revisions of "intel/xeon w/w-3265m"
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{{intel title|Xeon W-3265M}} | {{intel title|Xeon W-3265M}} | ||
{{chip | {{chip | ||
− | |||
|name=Xeon W-3265M | |name=Xeon W-3265M | ||
− | | | + | |image=cascade lake sp (xeon w) (front).png |
|designer=Intel | |designer=Intel | ||
|manufacturer=Intel | |manufacturer=Intel | ||
|model number=W-3265M | |model number=W-3265M | ||
− | |part number= | + | |part number=CD8069504248601 |
+ | |s-spec=SRFFJ | ||
|market=Workstation | |market=Workstation | ||
+ | |first announced=June 3, 2019 | ||
+ | |first launched=June 3, 2019 | ||
+ | |release price (tray)=$6,353.00 | ||
|family=Xeon W | |family=Xeon W | ||
|series=W-3200 | |series=W-3200 | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,700 MHz | |frequency=2,700 MHz | ||
+ | |turbo frequency1=4,400 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
|clock multiplier=27 | |clock multiplier=27 | ||
|isa=x86-64 | |isa=x86-64 | ||
|isa family=x86 | |isa family=x86 | ||
|microarch=Cascade Lake | |microarch=Cascade Lake | ||
− | |core name=Cascade Lake | + | |core name=Cascade Lake SP |
+ | |core stepping=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 24: | Line 32: | ||
|thread count=48 | |thread count=48 | ||
|max cpus=1 | |max cpus=1 | ||
+ | |max memory=2 TiB | ||
|tdp=205 W | |tdp=205 W | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''W-3265M''' is a {{arch|64}} [[24-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This | + | '''W-3265M''' is a {{arch|64}} [[24-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3265M operates at 2.7 GHz with a [[TDP]] of 205 W, a {{intel|turbo boost}} frequency of up to 4.4 GHz and a {{intel|turbo boost max}} of 4.6 GHz. This chip supports up to 2 TiB of hexa-channel DDR4-2933 memory. |
− | + | As indicated by the "''M''" suffix, this model has extended memory support of up to 2 TiB. | |
− | |||
+ | {{#set:intel turbo boost max technology 3 0 frequency=4.6 GHz}} | ||
== Cache == | == Cache == | ||
− | {{main|intel/microarchitectures/ | + | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} |
{{cache size | {{cache size | ||
|l1 cache=1.5 MiB | |l1 cache=1.5 MiB | ||
Line 58: | Line 67: | ||
|type=DDR4-2933 | |type=DDR4-2933 | ||
|ecc=Yes | |ecc=Yes | ||
− | |max mem= | + | |max mem=2 TiB |
|controllers=2 | |controllers=2 | ||
|channels=6 | |channels=6 | ||
Line 74: | Line 83: | ||
|type=PCIe | |type=PCIe | ||
|pcie revision=3.0 | |pcie revision=3.0 | ||
− | |pcie lanes= | + | |pcie lanes=64 |
|pcie config=x16 | |pcie config=x16 | ||
|pcie config 2=x8 | |pcie config 2=x8 | ||
Line 113: | Line 122: | ||
|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
Line 129: | Line 139: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
− | |tbmt3=No | + | |tbmt3=Yes |
+ | |tvb=No | ||
|bpt=No | |bpt=No | ||
|eist=Yes | |eist=Yes | ||
Line 162: | Line 174: | ||
|osguard=Yes | |osguard=Yes | ||
|intqat=No | |intqat=No | ||
+ | |dlboost=Yes | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 175: | Line 188: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
}} | }} | ||
+ | |||
+ | == Documents == | ||
+ | * [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]] |
Latest revision as of 23:26, 6 October 2019
Edit Values | |
Xeon W-3265M | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | W-3265M |
Part Number | CD8069504248601 |
S-Spec | SRFFJ |
Market | Workstation |
Introduction | June 3, 2019 (announced) June 3, 2019 (launched) |
Release Price | $6,353.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon W |
Series | W-3200 |
Locked | Yes |
Frequency | 2,700 MHz |
Turbo Frequency | 4,400 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 27 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Core Name | Cascade Lake SP |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 1-Way (Uniprocessor) |
Electrical | |
TDP | 205 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
W-3265M is a 64-bit 24-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3265M operates at 2.7 GHz with a TDP of 205 W, a turbo boost frequency of up to 4.4 GHz and a turbo boost max of 4.6 GHz. This chip supports up to 2 TiB of hexa-channel DDR4-2933 memory.
As indicated by the "M" suffix, this model has extended memory support of up to 2 TiB.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Documents[edit]
Facts about "Xeon W-3265M - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon W-3265M - Intel#pcie + |
base frequency | 2,700 MHz (2.7 GHz, 2,700,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
clock multiplier | 27 + |
core count | 24 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon W + |
first announced | June 3, 2019 + |
first launched | June 3, 2019 + |
full page name | intel/xeon w/w-3265m + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Deep Learning Boost + and Identity Protection Technology + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel identity protection technology support | true + |
has intel secure key technology | true + |
has intel speed shift technology | true + |
has intel supervisor mode execution protection | true + |
has intel trusted execution technology | true + |
has intel turbo boost max technology 3 0 | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
intel turbo boost max technology 3 0 frequency | 4,600 MHz (4.6 GHz, 4,600,000 kHz) + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + |
ldate | June 3, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Workstation + |
max cpu count | 1 + |
max memory | 2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) + |
max memory bandwidth | 131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
model number | W-3265M + |
name | Xeon W-3265M + |
number of avx-512 execution units | 2 + |
package | FCLGA-3647 + |
part number | CD8069504248601 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 6,353.00 (€ 5,717.70, £ 5,145.93, ¥ 656,455.49) + |
release price (tray) | $ 6,353.00 (€ 5,717.70, £ 5,145.93, ¥ 656,455.49) + |
s-spec | SRFFJ + |
series | W-3200 + |
smp max ways | 1 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2933 + |
tdp | 205 W (205,000 mW, 0.275 hp, 0.205 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency (1 core) | 4,400 MHz (4.4 GHz, 4,400,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |
x86/has memory protection extensions | true + |