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Difference between revisions of "intel/xeon w/w-3265"
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{{intel title|Xeon W-3265}}
 
{{intel title|Xeon W-3265}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon W-3265
 
|name=Xeon W-3265
−
|no image=Yes
+
|image=cascade lake sp (xeon w) (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=W-3265
 
|model number=W-3265
 
|part number=CD8069504153002
 
|part number=CD8069504153002
 +
|s-spec=SRFFE
 
|market=Workstation
 
|market=Workstation
 +
|first announced=June 3, 2019
 +
|first launched=June 3, 2019
 +
|release price (tray)=$3349.00
 
|family=Xeon W
 
|family=Xeon W
 
|series=W-3200
 
|series=W-3200
 
|locked=Yes
 
|locked=Yes
 
|frequency=2,700 MHz
 
|frequency=2,700 MHz
 +
|turbo frequency1=4,400 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 
|clock multiplier=27
 
|clock multiplier=27
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Cascade Lake
 
|microarch=Cascade Lake
−
|core name=Cascade Lake W
+
|core name=Cascade Lake SP
 +
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 24: Line 32:
 
|thread count=48
 
|thread count=48
 
|max cpus=1
 
|max cpus=1
 +
|max memory=1 TiB
 
|tdp=205 W
 
|tdp=205 W
 +
|package name 1=intel,fclga_3647
 
}}
 
}}
−
'''W-3265''' is a {{arch|64}} [[24-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processors, which is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture, operates at 2.7 GHz with a [[TDP]] of 205 W and a {{intel|turbo boost}} frequency of up to ? GHz.
+
'''W-3265''' is a {{arch|64}} [[24-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3265 operates at 2.7 GHz with a [[TDP]] of 205 W, a {{intel|turbo boost}} frequency of up to 4.4 GHz and a {{intel|turbo boost max}} of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.
−
 
 
−
 
 
−
{{unknown features}}
 
  
  
 +
{{#set:intel turbo boost max technology 3 0 frequency=4.6 GHz}}
 
== Cache ==
 
== Cache ==
−
{{main|intel/microarchitectures/skylake_(server)#Memory_Hierarchy|l1=Skylake § Cache}}
+
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 
{{cache size
 
{{cache size
 
|l1 cache=1.5 MiB
 
|l1 cache=1.5 MiB
Line 57: Line 65:
 
|type=DDR4-2933
 
|type=DDR4-2933
 
|ecc=Yes
 
|ecc=Yes
−
|max mem=768 TiB
+
|max mem=1 TiB
 
|controllers=2
 
|controllers=2
 
|channels=6
 
|channels=6
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|type=PCIe
 
|type=PCIe
 
|pcie revision=3.0
 
|pcie revision=3.0
−
|pcie lanes=48
+
|pcie lanes=64
 
|pcie config=x16
 
|pcie config=x16
 
|pcie config 2=x8
 
|pcie config 2=x8
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|pcie config 4=x1
 
|pcie config 4=x1
 
}}
 
}}
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,500 MHz
 +
|freq_1=4,600 MHz
 +
|freq_2=4,600 MHz
 +
|freq_3=4,400 MHz
 +
|freq_4=4,400 MHz
 +
|freq_5=4,100 MHz
 +
|freq_6=4,100 MHz
 +
|freq_7=4,100 MHz
 +
|freq_8=4,100 MHz
 +
|freq_9=4,100 MHz
 +
|freq_10=4,100 MHz
 +
|freq_11=4,100 MHz
 +
|freq_12=4,100 MHz
 +
|freq_13=3,900 MHz
 +
|freq_14=3,900 MHz
 +
|freq_15=3,900 MHz
 +
|freq_16=3,900 MHz
 +
|freq_17=3,600 MHz
 +
|freq_18=3,600 MHz
 +
|freq_19=3,600 MHz
 +
|freq_20=3,600 MHz
 +
|freq_21=3,400 MHz
 +
|freq_22=3,400 MHz
 +
|freq_23=3,400 MHz
 +
|freq_24=3,400 MHz
 
}}
 
}}
  
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|avx512vbmi=No
 
|avx512vbmi=No
 
|avx5124fmaps=No
 
|avx5124fmaps=No
 +
|avx512vnni=Yes
 
|avx5124vnniw=No
 
|avx5124vnniw=No
 
|avx512vpopcntdq=No
 
|avx512vpopcntdq=No
Line 128: Line 167:
 
|clmul=Yes
 
|clmul=Yes
 
|f16c=Yes
 
|f16c=Yes
 +
|bfloat16=No
 
|tbt1=No
 
|tbt1=No
 
|tbt2=Yes
 
|tbt2=Yes
−
|tbmt3=No
+
|tbmt3=Yes
 +
|tvb=No
 
|bpt=No
 
|bpt=No
 
|eist=Yes
 
|eist=Yes
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|osguard=Yes
 
|osguard=Yes
 
|intqat=No
 
|intqat=No
 +
|dlboost=Yes
 
|3dnow=No
 
|3dnow=No
 
|e3dnow=No
 
|e3dnow=No
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|sensemi=No
 
|sensemi=No
 
|xfr=No
 
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 
}}
 
}}
 +
 +
== Documents ==
 +
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]

Latest revision as of 14:24, 31 October 2019

Edit Values
Xeon W-3265
cascade lake sp (xeon w) (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberW-3265
Part NumberCD8069504153002
S-SpecSRFFE
MarketWorkstation
IntroductionJune 3, 2019 (announced)
June 3, 2019 (launched)
Release Price$3349.00 (tray)
ShopAmazon
General Specs
FamilyXeon W
SeriesW-3200
LockedYes
Frequency2,700 MHz
Turbo Frequency4,400 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier27
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
Core NameCascade Lake SP
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores24
Threads48
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP205 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

W-3265 is a 64-bit 24-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3265 operates at 2.7 GHz with a TDP of 205 W, a turbo boost frequency of up to 4.4 GHz and a turbo boost max of 4.6 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associative 
L1D$768 KiB
786,432 B
0.75 MiB
24x32 KiB8-way set associativewrite-back
L2$24 MiB
24,576 KiB
25,165,824 B
0.0234 GiB
  24x1 MiB16-way set associativewrite-back
L3$33 MiB
33,792 KiB
34,603,008 B
0.0322 GiB
  24x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 64
Configuration: x16, x8, x4, x1


Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
123456789101112131415161718192021222324
Normal2,500 MHz4,600 MHz4,600 MHz4,400 MHz4,400 MHz4,100 MHz4,100 MHz4,100 MHz4,100 MHz4,100 MHz4,100 MHz4,100 MHz4,100 MHz3,900 MHz3,900 MHz3,900 MHz3,900 MHz3,600 MHz3,600 MHz3,600 MHz3,600 MHz3,400 MHz3,400 MHz3,400 MHz3,400 MHz

Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
TBMT 3.0Turbo Boost Max Technology 3.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
DL BoostDeep Learning Boost
IPTIdentity Protection Technology

Documents[edit]

Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_w/w-3265&oldid=94231"
Facts about "Xeon W-3265 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon W-3265 - Intel#pcie +
base frequency2,700 MHz (2.7 GHz, 2,700,000 kHz) +
clock multiplier27 +
core count24 +
core nameCascade Lake W +
designerIntel +
familyXeon W +
full page nameintel/xeon w/w-3265 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard + and Identity Protection Technology +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size768 KiB (786,432 B, 0.75 MiB) +
l1i$ description8-way set associative +
l1i$ size768 KiB (786,432 B, 0.75 MiB) +
l2$ description16-way set associative +
l2$ size24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) +
l3$ description11-way set associative +
l3$ size33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) +
ldate3000 +
manufacturerIntel +
market segmentWorkstation +
max cpu count1 +
max memory bandwidth131.13 GiB/s (134,277.12 MiB/s, 140.8 GB/s, 140,799.765 MB/s, 0.128 TiB/s, 0.141 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model numberW-3265 +
nameXeon W-3265 +
number of avx-512 execution units2 +
part numberCD8069504153002 +
process14 nm (0.014 μm, 1.4e-5 mm) +
seriesW-3200 +
smp max ways1 +
supported memory typeDDR4-2933 +
tdp205 W (205,000 mW, 0.275 hp, 0.205 kW) +
technologyCMOS +
thread count48 +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +