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{{intel title|Xeon W-3223}}
 
{{intel title|Xeon W-3223}}
 
{{chip
 
{{chip
−
|future=Yes
 
 
|name=Xeon W-3223
 
|name=Xeon W-3223
−
|image=intel skylake w (front).png
+
|image=cascade lake sp (xeon w) (front).png
 
|designer=Intel
 
|designer=Intel
 
|manufacturer=Intel
 
|manufacturer=Intel
 
|model number=W-3223
 
|model number=W-3223
 
|part number=CD8069504248402
 
|part number=CD8069504248402
 +
|s-spec=SRFFG
 
|market=Workstation
 
|market=Workstation
 +
|first announced=June 3, 2019
 +
|first launched=June 3, 2019
 +
|release price (tray)=$749.00
 
|family=Xeon W
 
|family=Xeon W
 
|series=W-3200
 
|series=W-3200
 
|locked=Yes
 
|locked=Yes
 
|frequency=3,500 MHz
 
|frequency=3,500 MHz
 +
|turbo frequency1=4,000 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 
|clock multiplier=35
 
|clock multiplier=35
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
 
|microarch=Cascade Lake
 
|microarch=Cascade Lake
−
|core name=Cascade Lake W
+
|core name=Cascade Lake SP
 +
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 24: Line 32:
 
|thread count=16
 
|thread count=16
 
|max cpus=1
 
|max cpus=1
 +
|max memory=1 TiB
 +
|tdp=160 W
 +
|package name 1=intel,fclga_3647
 +
}}
 +
'''W-3223''' is a {{arch|64}} [[octa-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3223 operates at 3.5 GHz with a [[TDP]] of 160 W, a {{intel|turbo boost}} frequency of up to 4 GHz and a {{intel|turbo boost max}} of 4.2 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2666 memory.
 +
 +
 +
{{#set:intel turbo boost max technology 3 0 frequency=4.2 GHz}}
 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 +
This processor has a non-default [[level 3 cache]] of 16.5 MiB, an amount usually found in the [[12 cores]] part.
 +
{{cache size
 +
|l1 cache=512 KiB
 +
|l1i cache=256 KiB
 +
|l1i break=8x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=256 KiB
 +
|l1d break=8x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=8x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=16.5 MiB
 +
|l3 break=12x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
 +
}}
 +
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=119.21 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
|bandwidth hchan=119.21 GiB/s
 +
}}
 +
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=64
 +
|pcie config=x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
|pcie config 4=x1
 +
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=2
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=Yes
 +
|tvb=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=No
 +
|kpt=No
 +
|ptt=No
 +
|intelrunsure=No
 +
|mbe=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Documents ==
 +
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=3,500 MHz
 +
|freq_1=4,000 MHz
 +
|freq_2=4,000 MHz
 +
|freq_3=3,800 MHz
 +
|freq_4=3,800 MHz
 +
|freq_5=3,800 MHz
 +
|freq_6=3,800 MHz
 +
|freq_7=3,800 MHz
 +
|freq_8=3,800 MHz
 +
|freq_avx2_1=3,800 MHz
 +
|freq_avx2_2=3,800 MHz
 +
|freq_avx2_3=3,600 MHz
 +
|freq_avx2_4=3,600 MHz
 +
|freq_avx2_5=3,500 MHz
 +
|freq_avx2_6=3,500 MHz
 +
|freq_avx2_7=3,500 MHz
 +
|freq_avx2_8=3,500 MHz
 +
|freq_avx512_1=3,300 MHz
 +
|freq_avx512_2=3,300 MHz
 +
|freq_avx512_3=3,100 MHz
 +
|freq_avx512_4=3,100 MHz
 +
|freq_avx512_5=3,000 MHz
 +
|freq_avx512_6=3,000 MHz
 +
|freq_avx512_7=3,000 MHz
 +
|freq_avx512_8=3,000 MHz
 
}}
 
}}

Latest revision as of 04:36, 30 October 2019

Edit Values
Xeon W-3223
cascade lake sp (xeon w) (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberW-3223
Part NumberCD8069504248402
S-SpecSRFFG
MarketWorkstation
IntroductionJune 3, 2019 (announced)
June 3, 2019 (launched)
Release Price$749.00 (tray)
ShopAmazon
General Specs
FamilyXeon W
SeriesW-3200
LockedYes
Frequency3,500 MHz
Turbo Frequency4,000 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier35
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
Core NameCascade Lake SP
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP160 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

W-3223 is a 64-bit octa-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3223 operates at 3.5 GHz with a TDP of 160 W, a turbo boost frequency of up to 4 GHz and a turbo boost max of 4.2 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2666 memory.


Cache[edit]

Main article: Cascade Lake § Cache

This processor has a non-default level 3 cache of 16.5 MiB, an amount usually found in the 12 cores part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$16.5 MiB
16,896 KiB
17,301,504 B
0.0161 GiB
  12x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth119.21 GiB/s
122,071.04 MiB/s
128.001 GB/s
128,000.763 MB/s
0.116 TiB/s
0.128 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
Hexa 119.21 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 64
Configuration: x16, x8, x4, x1


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
TBMT 3.0Turbo Boost Max Technology 3.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
DL BoostDeep Learning Boost
IPTIdentity Protection Technology

Documents[edit]

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal3,500 MHz4,000 MHz4,000 MHz3,800 MHz3,800 MHz3,800 MHz3,800 MHz3,800 MHz3,800 MHz
AVX23,800 MHz3,800 MHz3,600 MHz3,600 MHz3,500 MHz3,500 MHz3,500 MHz3,500 MHz
AVX5123,300 MHz3,300 MHz3,100 MHz3,100 MHz3,000 MHz3,000 MHz3,000 MHz3,000 MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_w/w-3223&oldid=94223"
Facts about "Xeon W-3223 - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon W-3223 - Intel#pcie +
base frequency3,500 MHz (3.5 GHz, 3,500,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
clock multiplier35 +
core count8 +
core nameCascade Lake SP +
core steppingB1 +
designerIntel +
familyXeon W +
first announcedJune 3, 2019 +
first launchedJune 3, 2019 +
full page nameintel/xeon w/w-3223 +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has advanced vector extensions 512true +
has ecc memory supporttrue +
has extended page tables supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Turbo Boost Max Technology 3.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions +, Memory Protection Extensions +, Secure Key Technology +, OS Guard +, Deep Learning Boost + and Identity Protection Technology +
has intel deep learning boosttrue +
has intel enhanced speedstep technologytrue +
has intel identity protection technology supporttrue +
has intel secure key technologytrue +
has intel speed shift technologytrue +
has intel supervisor mode execution protectiontrue +
has intel trusted execution technologytrue +
has intel turbo boost max technology 3 0true +
has intel turbo boost technology 2 0true +
has intel vpro technologytrue +
has intel vt-d technologytrue +
has intel vt-x technologytrue +
has locked clock multipliertrue +
has second level address translation supporttrue +
has simultaneous multithreadingtrue +
has transactional synchronization extensionstrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
intel turbo boost max technology 3 0 frequency4,200 MHz (4.2 GHz, 4,200,000 kHz) +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size16.5 MiB (16,896 KiB, 17,301,504 B, 0.0161 GiB) +
ldateJune 3, 2019 +
main imageFile:cascade lake sp (xeon w) (front).png +
manufacturerIntel +
market segmentWorkstation +
max cpu count1 +
max memory1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth119.21 GiB/s (122,071.04 MiB/s, 128.001 GB/s, 128,000.763 MB/s, 0.116 TiB/s, 0.128 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
model numberW-3223 +
nameXeon W-3223 +
number of avx-512 execution units2 +
packageFCLGA-3647 +
part numberCD8069504248402 +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
release price (tray)$ 749.00 (€ 674.10, £ 606.69, ¥ 77,394.17) +
s-specSRFFG +
seriesW-3200 +
smp max ways1 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2666 +
tdp160 W (160,000 mW, 0.215 hp, 0.16 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)4,000 MHz (4 GHz, 4,000,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +
x86/has memory protection extensionstrue +