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{{intel title|Xeon W-3235}}
 
{{intel title|Xeon W-3235}}
−
{{chip}}
+
{{chip
 +
|name=Xeon W-3235
 +
|image=cascade lake sp (xeon w) (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=W-3235
 +
|part number=CD8069504152802
 +
|s-spec=SRFFC
 +
|market=Workstation
 +
|first announced=June 3, 2019
 +
|first launched=June 3, 2019
 +
|release price (tray)=$1,398.00
 +
|family=Xeon W
 +
|series=W-3200
 +
|locked=Yes
 +
|frequency=3,300 MHz
 +
|turbo frequency1=4,400 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=33
 +
|isa=x86-64
 +
|isa family=x86
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|microarch=Cascade Lake
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|core name=Cascade Lake SP
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|core stepping=B1
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|process=14 nm
 +
|technology=CMOS
 +
|word size=64 bit
 +
|core count=12
 +
|thread count=24
 +
|max cpus=1
 +
|max memory=1 TiB
 +
|tdp=180 W
 +
|package name 1=intel,fclga_3647
 +
}}
 +
'''W-3235''' is a {{arch|64}} [[dodeca-core]] [[x86]] enterprise performance workstation microprocessor introduced by [[Intel]] in [[2019]]. This processor is fabricated on an enhanced [[14 nm process|14nm++ process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture. The W-3235 operates at 3.3 GHz with a [[TDP]] of 180 W, a {{intel|turbo boost}} frequency of up to 4.4 GHz and a {{intel|turbo boost max}} of 4.5 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.
 +
 
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{{#set:intel turbo boost max technology 3 0 frequency=4.5 GHz}}
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== Cache ==
 +
{{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
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This processor has a non-default [[level 3 cache]] of 19.25 MiB, an amount usually found in the [[14 cores]] part.
 +
{{cache size
 +
|l1 cache=768 KiB
 +
|l1i cache=384 KiB
 +
|l1i break=12x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=384 KiB
 +
|l1d break=12x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=12 MiB
 +
|l2 break=12x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=19.25 MiB
 +
|l3 break=14x1.375 MiB
 +
|l3 desc=11-way set associative
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|l3 policy=write-back
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}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2933
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=2
 +
|channels=6
 +
|max bandwidth=131.13 GiB/s
 +
|bandwidth schan=21.86 GiB/s
 +
|bandwidth dchan=43.71 GiB/s
 +
|bandwidth qchan=87.42 GiB/s
 +
|bandwidth hchan=131.13 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=64
 +
|pcie config=x16
 +
|pcie config 2=x8
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|pcie config 3=x4
 +
|pcie config 4=x1
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
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|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|avx512units=2
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
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|xop=No
 +
|adx=Yes
 +
|clmul=Yes
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|f16c=Yes
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|bfloat16=No
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|tbt1=No
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|tbt2=Yes
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|tbmt3=Yes
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|tvb=No
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|bpt=No
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|eist=Yes
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|sst=Yes
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|flex=No
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|fastmem=No
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|ivmd=Yes
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|intelnodecontroller=No
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|intelnode=No
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|kpt=No
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|ptt=No
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|intelrunsure=No
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|mbe=No
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|isrt=No
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|sba=No
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|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=Yes
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=Yes
 +
|sgx=No
 +
|securekey=Yes
 +
|osguard=Yes
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 
 +
== Documents ==
 +
* [[:File:w-3200-pb.pdf|Xeon W-3200 Series Product Brief]]

Latest revision as of 23:25, 6 October 2019

Edit Values
Xeon W-3235
cascade lake sp (xeon w) (front).png
General Info
DesignerIntel
ManufacturerIntel
Model NumberW-3235
Part NumberCD8069504152802
S-SpecSRFFC
MarketWorkstation
IntroductionJune 3, 2019 (announced)
June 3, 2019 (launched)
Release Price$1,398.00 (tray)
ShopAmazon
General Specs
FamilyXeon W
SeriesW-3200
LockedYes
Frequency3,300 MHz
Turbo Frequency4,400 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier33
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
Core NameCascade Lake SP
Core SteppingB1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores12
Threads24
Max Memory1 TiB
Multiprocessing
Max SMP1-Way (Uniprocessor)
Electrical
TDP180 W
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647

W-3235 is a 64-bit dodeca-core x86 enterprise performance workstation microprocessor introduced by Intel in 2019. This processor is fabricated on an enhanced 14nm++ process based on the Cascade Lake microarchitecture. The W-3235 operates at 3.3 GHz with a TDP of 180 W, a turbo boost frequency of up to 4.4 GHz and a turbo boost max of 4.5 GHz. This chip supports up to 1 TiB of hexa-channel DDR4-2933 memory.


Cache[edit]

Main article: Cascade Lake § Cache

This processor has a non-default level 3 cache of 19.25 MiB, an amount usually found in the 14 cores part.

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associative 
L1D$384 KiB
393,216 B
0.375 MiB
12x32 KiB8-way set associativewrite-back
L2$12 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
  12x1 MiB16-way set associativewrite-back
L3$19.25 MiB
19,712 KiB
20,185,088 B
0.0188 GiB
  14x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth131.13 GiB/s
134,277.12 MiB/s
140.8 GB/s
140,799.765 MB/s
0.128 TiB/s
0.141 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Hexa 131.13 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 64
Configuration: x16, x8, x4, x1


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit (2 Units)
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
TBMT 3.0Turbo Boost Max Technology 3.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
MPXMemory Protection Extensions
Secure KeySecure Key Technology
SMEPOS Guard Technology
VMDVolume Management Device
DL BoostDeep Learning Boost
IPTIdentity Protection Technology

Documents[edit]

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