Semiconductor & Computer Engineering
(→3100-Series (Skylake)) |
(→3200-Series (Cascade Lake)) |
||
| (3 intermediate revisions by the same user not shown) | |||
| Line 28: | Line 28: | ||
| successor link = | | successor link = | ||
}} | }} | ||
| − | '''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server microprocessors introduced by [[Intel]] in 2017. | + | '''Xeon Bronze''' is a family of {{arch|64}} [[x86]] dual-socket multi-core entry-level server-class microprocessors introduced by [[Intel]] in 2017. |
== Overview == | == Overview == | ||
| Line 36: | Line 36: | ||
=== 3100-Series (Skylake) === | === 3100-Series (Skylake) === | ||
{{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | {{see also|intel/microarchitectures/skylake (server)|l1=Skylake µarch}} | ||
| − | First-generation Xeon Bronze | + | First-generation Xeon Bronze processors were introduced in July 2017. Those chips were fabricated on a enhanced [[14 nm process|14nm+ process]] based on the {{intel|Skylake (server)|Skylake|l=arch}} microarchitecture which brought a {{intel|Skylake (Server)#Key changes from Broadwell|l=arch|relatively large}} SoC design change from the prior Xeon families. Those processors were the first to move to a {{intel|mesh interconnect}} which introduced a tile-based architecture, bringing the first implementation of {{x86|AVX-512}} along with a rearchitected cache hierarchy designed for server workloads. All of the bronze 3100-series microprocessors feature dual-socket capabilities with up to [[8 cores]] and 8 threads. Additionally, all Xeon Bronze processors support: |
| + | * '''Proc:''' [[14 nm process]] | ||
* '''TDP:''' 85 W | * '''TDP:''' 85 W | ||
* '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. | * '''Mem:''' 768 GiB hexa-channel DDR4-2133 ECC memory. | ||
| − | * '''I/O:''' 48 PCIe 3 lanes | + | * '''I/O:''' 48 PCIe Gen 3.0 lanes |
* '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}) | * '''ISA:''' Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, {{x86|AVX-512}}-{{x86|AVX512F|F}}/{{x86|AVX512CD|CD}}/{{x86|AVX512BW|BW}}/{{x86|AVX512DQ|DQ}}/{{x86|AVX512VL|VL}}) | ||
* '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | * '''Features:''' {{intel|Speed Shift}}, {{intel|vPro}}, {{intel|VT-x}}, {{intel|TSX}}, {{intel|TXT}}, {{intel|Volume Management Device}} (VMD), {{intel|Mode-based Execute Control}} (MBE), {{intel|Key Protection Technology}} (KPT), and {{intel|Platform Trust Technology}} (PTT). | ||
| Line 79: | Line 80: | ||
=== 3200-Series (Cascade Lake) === | === 3200-Series (Cascade Lake) === | ||
{{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}} | {{see also|intel/microarchitectures/cascade lake|l1=Cascade Lake µarch}} | ||
| − | Second-generation Xeon Scalable Bronze was introduced in early | + | Second-generation Xeon Scalable Bronze was introduced in early 2019. Those processors are fabricated on an enhanced [[14 nm process]] based on the {{intel|Cascade Lake|l=arch}} microarchitecture which allows for higher clock speeds and introduced a {{intel|Cascade Lake#Key changes from Skylake|l=arch|number of}} hardware changes against the various [[speculative execution]] [[side channel analysis|vulnerabilities]]. Those processors also introduced new {{x86|AVX-512 VNNI|new instructions}} for the [[acceleration]] of machine learning (inference) as well as support for [[persistent memory]]. All 3200-series Xeon Bronze processors support: |
* '''TDP:''' 85 W | * '''TDP:''' 85 W | ||
Latest revision as of 13:08, 2 June 2019
| Xeon Bronze | |
.png)
| |
| Xeon Bronze Logo | |
| Developer | Intel |
| Manufacturer | Intel |
| Type | Microprocessors |
| Introduction | May 4, 2017 (announced) July 11, 2017 (launch) |
| Architecture | x86 server multiprocessors |
| ISA | x86-64 |
| µarch | Skylake |
| Word size | 64 bit 8 octets
16 nibbles |
| Process | 14 nm 0.014 μm
1.4e-5 mm |
| Technology | CMOS |
| Package | FCLGA-3647 |
| Socket | LGA-3647 |
| Succession | |
| ← | |
| Xeon E7 Xeon E5 |
|
Xeon Bronze is a family of 64-bit x86 dual-socket multi-core entry-level server-class microprocessors introduced by Intel in 2017.
Overview[edit]
Released in July 2017, the Xeon Bronze are the successor to the Xeon E5/E7 families. Xeon Bronze is geared toward entry-level dual-socket server and workstation microprocessors. Those processors are ideally positioned for price-sensitive applications which require light-range workloads with enhanced security features and large memory. Additionally, those processors incorporate a number of Ultra Path Interconnect (UPI) links. Unlike the higher tier Xeon families, the Xeon Bronze doesn't have Turbo Boost Technology or Hyper-Threading support.
Members[edit]
3100-Series (Skylake)[edit]
- See also: Skylake µarch
First-generation Xeon Bronze processors were introduced in July 2017. Those chips were fabricated on a enhanced 14nm+ process based on the Skylake microarchitecture which brought a relatively large SoC design change from the prior Xeon families. Those processors were the first to move to a mesh interconnect which introduced a tile-based architecture, bringing the first implementation of AVX-512 along with a rearchitected cache hierarchy designed for server workloads. All of the bronze 3100-series microprocessors feature dual-socket capabilities with up to 8 cores and 8 threads. Additionally, all Xeon Bronze processors support:
- Proc: 14 nm process
- TDP: 85 W
- Mem: 768 GiB hexa-channel DDR4-2133 ECC memory.
- I/O: 48 PCIe Gen 3.0 lanes
- ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX-512-F/CD/BW/DQ/VL)
- Features: Speed Shift, vPro, VT-x, TSX, TXT, Volume Management Device (VMD), Mode-based Execute Control (MBE), Key Protection Technology (KPT), and Platform Trust Technology (PTT).
All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 Ultra Path Interconnect (UPI) links.
| List of Skylake-based Xeon Bronze Processors | ||||||||
|---|---|---|---|---|---|---|---|---|
| Model | Price | Launched | Cores | Threads | Frequency | TDP | L2$ | L3$ |
| 3104 | $ 213.00 € 191.70 £ 172.53 ¥ 22,009.29 | 11 July 2017 | 6 | 6 | 1.7 GHz 1,700 MHz 1,700,000 kHz | 85 W 85,000 mW 0.114 hp 0.085 kW | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB | 8.25 MiB 8,448 KiB 8,650,752 B 0.00806 GiB |
| 3106 | $ 306.00 € 275.40 £ 247.86 ¥ 31,618.98 | 11 July 2017 | 8 | 8 | 1.7 GHz 1,700 MHz 1,700,000 kHz | 85 W 85,000 mW 0.114 hp 0.085 kW | 8 MiB 8,192 KiB 8,388,608 B 0.00781 GiB | 11 MiB 11,264 KiB 11,534,336 B 0.0107 GiB |
| Count: 2 | ||||||||
3200-Series (Cascade Lake)[edit]
- See also: Cascade Lake µarch
Second-generation Xeon Scalable Bronze was introduced in early 2019. Those processors are fabricated on an enhanced 14 nm process based on the Cascade Lake microarchitecture which allows for higher clock speeds and introduced a number of hardware changes against the various speculative execution vulnerabilities. Those processors also introduced new new instructions for the acceleration of machine learning (inference) as well as support for persistent memory. All 3200-series Xeon Bronze processors support:
- TDP: 85 W
- Mem: 1 TiB hexa-channel DDR4-2133 ECC memory.
- I/O: 48 PCIe 3 lanes
- ISA: Everything up to AVX-512 (SMM, FPU, NX, MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AES, AVX, FMA3, AVX2, AVX-512-F/CD/BW/DQ/VL/VNNI)
- Features: Speed Shift, vPro, VT-x, TSX, TXT, Volume Management Device (VMD), Mode-based Execute Control (MBE), Key Protection Technology (KPT), and Platform Trust Technology (PTT).
All Xeon Bronze processors support QuickAssist Technology which is integrated on the chipset as well as the Omni-Path Architecture on the chipset as well as via discrete PCIe cards. All models also support 2 Ultra Path Interconnect (UPI) links.
| List of Cascade Lake-based Xeon Bronze Processors | ||||||||
|---|---|---|---|---|---|---|---|---|
| Model | Price | Launched | Cores | Threads | Frequency | TDP | L2$ | L3$ |
| 3204 | $ 213.00 € 191.70 , $ 224.00£ 172.53 ¥ 22,009.29 € 201.60 £ 181.44 ¥ 23,145.92 | 2 April 2019 | 6 | 6 | 1.9 GHz 1,900 MHz 1,900,000 kHz | 85 W 85,000 mW 0.114 hp 0.085 kW | 6 MiB 6,144 KiB 6,291,456 B 0.00586 GiB | 8.25 MiB 8,448 KiB 8,650,752 B 0.00806 GiB |
| Count: 1 | ||||||||
See also[edit]
| designer | Intel + |
| first announced | May 4, 2017 + |
| first launched | July 11, 2017 + |
| full page name | intel/xeon bronze + |
| instance of | microprocessor family + |
| instruction set architecture | x86-64 + |
| main designer | Intel + |
| manufacturer | Intel + |
| microarchitecture | Skylake + |
| name | Xeon Bronze + |
| package | FCLGA-3647 + |
| process | 14 nm (0.014 μm, 1.4e-5 mm) + |
| socket | LGA-3647 + |
| technology | CMOS + |
| word size | 64 bit (8 octets, 16 nibbles) + |