Semiconductor & Computer Engineering
(change compute die into base die because it is a error) |
|||
| (4 intermediate revisions by one other user not shown) | |||
| Line 22: | Line 22: | ||
== Architecture == | == Architecture == | ||
| − | * [[ | + | [[File:intel lakefield overview.png|right|thumb|Lakefield Architectre]] |
| + | * [[3D integrated circuit]] | ||
** {{intel|Foveros}} packaging | ** {{intel|Foveros}} packaging | ||
** [[22 nm]] base field | ** [[22 nm]] base field | ||
** [[10 nm]] compute field | ** [[10 nm]] compute field | ||
| − | *** 1x {{\\|Sunny Cove}} [[big core]] | + | *** single-ISA heterogeneous multi-core |
| − | *** 4x {{\\|Tremont}} [[small cores]] | + | **** 1x {{\\|Sunny Cove}} [[big core]] |
| + | **** 4x {{\\|Tremont}} [[small cores]] | ||
* GPU | * GPU | ||
** {{\\|Gen11}} graphics | ** {{\\|Gen11}} graphics | ||
| + | ** {{\\|Gen11}}.5 display engine | ||
| + | * IPU | ||
| + | ** IPU 5.5 | ||
* Memory | * Memory | ||
** LPDDR4X up to 4266 MT/s | ** LPDDR4X up to 4266 MT/s | ||
** POP DRAM | ** POP DRAM | ||
| + | * Power | ||
| + | ** 5 W and 7 W TDPs | ||
| + | |||
| + | === Block diagram === | ||
| + | {{empty section}} | ||
== Overview == | == Overview == | ||
| − | {{ | + | Lakefield is [[Intel's]] first production [[three-dimensional integrated circuit]] single-[[ISA]] [[penta-core]] [[heterogeneous multi-core architecture]]. The SoC features a compute die that rests directly on a base die using Intel's {{intel|Foveros}} face-to-face 3D integration technology. The [[package on package|PoP]] memory then sits on top of the compute die connected via [[wirebond]]. The entire SoC is a single package measuring 12 mm by 12 mm by 1 mm. |
| + | |||
| + | Lakefield started as an initiative from Intel to create a new class of compute devices with high performance in a mobile phone form factor. To that end, Lakefield barrows requirements from both desktop/laptop and smartphone including high-performance cores, always-on capabilities, always-on connectivity, and ultra-low 2-3 milliwatts range standby power. Lakefield main compute die is fabricated on Intel's [[intel 10nm|10 nm process]] for it's high-power and efficiency capabilities while the base die is fabricated on the company's [[22FFL|22 nm (22FFL) process]] for its ultra-low power capabilities. Lakefield provides a gen-over-gen improvement of 1/10th the standby power, 50% graphics performance improvement, 40% total core area reduction, and 40% Z-height reduction. | ||
| + | |||
| + | == Compute die == | ||
| + | The compute die is fabricated on Intel's [[intel 10nm|10 nm process]] for high performance and high power efficiency. This die features all the compute-related IPs. It incorporates a single {{\\|Sunny Cove}} [[big core]] along with a quad-core cluster of {{\\|Tremont}} [[small cores]]. This die also integrates IPU 5.5, {{\\|Gen11}} graphics and media along with a Gen11.5 display engine, and quad-channel (16-bit) LPDDR4x memory. The IPU 5.5 supports up to 6 connected camera at 16 MP while the Gen 11.5 display supports 4 pipes and two displays with a 5K @ 60 Hz or 4K @ 120 Hz resolution. | ||
| + | |||
| + | === Heterogeneous cores === | ||
| + | {{see also|intel/microarchitectures/sunny cove|intel/microarchitectures/tremont|l1=Sunny Cove|l2=Tremont}} | ||
| + | [[File:lkf big vs small st.jpg|thumb|right|{{\\|Sunny Cove}} vs {{\\|Tremont}} core in ST perf]] | ||
| + | [[File:lkf big vs small mt.jpg|thumb|right|{{\\|Sunny Cove}} vs 4x{{\\|Tremont}} cores in MT perf]] | ||
| + | Lakefield compute die features a hybrid architecture with single big core along with four small cores. The architecture utilizes a single-ISA, thus having {{x86|AVX}} and {{x86|AVX-512}} disabled on the big cores in order to enable a seamless migration of workloads between cores. The big {{\\|Sunny Cove}} core is designed for high-performance and bursty workloads while light-weight and threaded applications can utilize the {{\\|Tremont}} cores for higher power-efficiency. The combination of both types of cores allow for a wider power/performance curve beyond what is possible with just a single type of core. | ||
| + | |||
| + | On Intel's 10-nanometer process, four {{\\|Tremont}} cores along with their 1.5 MiB of [[L2 cache]] fit within the silicon area of a single {{\\|Sunny Cove}} core. The single {{\\|Sunny cove}} core yields the best power-performance efficiency at the higher end of the perf/power curve but loses to the {{\\|Tremont}} core at the low-end. Likewise, the four {{\\|Tremont}} cores can extend the multi-thread capabilities by over 100% over the {{\\|Sunny Cove}} core while doing so at much higher power efficiency. | ||
| + | |||
| + | Lakefield dynamically provides feedback to the OS/SW regarding the power and performance characteristics of the workload. Workloads that exhibit performance or high responsiveness are given an indication to get scheduled on the {{\\|Sunny Cove}} cores. Likewise, background threads are given an indication to get scheduled on the {{\\|Tremont}} cores. The feedback can be used for the OS to dynamically migrate threads to provide the best power and power efficiency. | ||
| + | |||
| + | == Base die == | ||
| + | The BASE die is designed for ultra-low power always-on capabilities. This die integrates power delivery, security, storage, audio, USB 2 and 3, UFS3, PCIe Gen3, ISH, I3C, SDIO, CSE, TC SS, SPI/I2C. | ||
| + | |||
| + | == Power delivery == | ||
| + | Lakefield uses a [[power management integrated circuit]] (PMIC) instead of a discrete [[voltage regulator module|VR]] or [[fully-integrated voltage regulator|FIVR]] as with its contemporaries such as {{\\|Ice Lake (client)|Ice Lake}}. To support Lakefield, two PMICs are required - one PMIC for the compute die and one for the base die (CSC and WRC). | ||
| + | |||
| + | == Bibliography == | ||
| + | * {{bib|hc|31|Intel}} | ||
Latest revision as of 05:44, 14 August 2021
| Edit Values | |
| Lakefield µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | Intel |
| Manufacturer | Intel |
| Introduction | 2019 |
| Process | 22 nm, 10 nm |
| Core Configs | 5 |
| Pipeline | |
| Type | Superscalar, Superpipeline |
| OoOE | Yes |
| Speculative | Yes |
| Reg Renaming | Yes |
| Instructions | |
| ISA | x86-64 |
| Cache | |
| L2 Cache | 512 KiB + 1.5 MiB |
| L3 Cache | 4 MiB/chip |
Lakefield (LKF) is a high-performance low-power 3D microarchitecture designed by Intel and introduced in 2019.
Contents
Architecture[edit]
- 3D integrated circuit
- Foveros packaging
- 22 nm base field
- 10 nm compute field
- single-ISA heterogeneous multi-core
- 1x Sunny Cove big core
- 4x Tremont small cores
- single-ISA heterogeneous multi-core
- GPU
- IPU
- IPU 5.5
- Memory
- LPDDR4X up to 4266 MT/s
- POP DRAM
- Power
- 5 W and 7 W TDPs
Block diagram[edit]
 |
This section is empty; you can help add the missing info by editing this page. |
Overview[edit]
Lakefield is Intel's first production three-dimensional integrated circuit single-ISA penta-core heterogeneous multi-core architecture. The SoC features a compute die that rests directly on a base die using Intel's Foveros face-to-face 3D integration technology. The PoP memory then sits on top of the compute die connected via wirebond. The entire SoC is a single package measuring 12 mm by 12 mm by 1 mm.
Lakefield started as an initiative from Intel to create a new class of compute devices with high performance in a mobile phone form factor. To that end, Lakefield barrows requirements from both desktop/laptop and smartphone including high-performance cores, always-on capabilities, always-on connectivity, and ultra-low 2-3 milliwatts range standby power. Lakefield main compute die is fabricated on Intel's 10 nm process for it's high-power and efficiency capabilities while the base die is fabricated on the company's 22 nm (22FFL) process for its ultra-low power capabilities. Lakefield provides a gen-over-gen improvement of 1/10th the standby power, 50% graphics performance improvement, 40% total core area reduction, and 40% Z-height reduction.
Compute die[edit]
The compute die is fabricated on Intel's 10 nm process for high performance and high power efficiency. This die features all the compute-related IPs. It incorporates a single Sunny Cove big core along with a quad-core cluster of Tremont small cores. This die also integrates IPU 5.5, Gen11 graphics and media along with a Gen11.5 display engine, and quad-channel (16-bit) LPDDR4x memory. The IPU 5.5 supports up to 6 connected camera at 16 MP while the Gen 11.5 display supports 4 pipes and two displays with a 5K @ 60 Hz or 4K @ 120 Hz resolution.
Heterogeneous cores[edit]
- See also: Sunny Cove and Tremont
Lakefield compute die features a hybrid architecture with single big core along with four small cores. The architecture utilizes a single-ISA, thus having AVX and AVX-512 disabled on the big cores in order to enable a seamless migration of workloads between cores. The big Sunny Cove core is designed for high-performance and bursty workloads while light-weight and threaded applications can utilize the Tremont cores for higher power-efficiency. The combination of both types of cores allow for a wider power/performance curve beyond what is possible with just a single type of core.
On Intel's 10-nanometer process, four Tremont cores along with their 1.5 MiB of L2 cache fit within the silicon area of a single Sunny Cove core. The single Sunny cove core yields the best power-performance efficiency at the higher end of the perf/power curve but loses to the Tremont core at the low-end. Likewise, the four Tremont cores can extend the multi-thread capabilities by over 100% over the Sunny Cove core while doing so at much higher power efficiency.
Lakefield dynamically provides feedback to the OS/SW regarding the power and performance characteristics of the workload. Workloads that exhibit performance or high responsiveness are given an indication to get scheduled on the Sunny Cove cores. Likewise, background threads are given an indication to get scheduled on the Tremont cores. The feedback can be used for the OS to dynamically migrate threads to provide the best power and power efficiency.
Base die[edit]
The BASE die is designed for ultra-low power always-on capabilities. This die integrates power delivery, security, storage, audio, USB 2 and 3, UFS3, PCIe Gen3, ISH, I3C, SDIO, CSE, TC SS, SPI/I2C.
Power delivery[edit]
Lakefield uses a power management integrated circuit (PMIC) instead of a discrete VR or FIVR as with its contemporaries such as Ice Lake. To support Lakefield, two PMICs are required - one PMIC for the compute die and one for the base die (CSC and WRC).
Bibliography[edit]
- Intel, IEEE Hot Chips 31 Symposium (HCS) 2019.
| codename | Lakefield + |
| core count | 5 + |
| designer | Intel + |
| first launched | 2019 + |
| full page name | intel/microarchitectures/lakefield + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | Intel + |
| microarchitecture type | CPU + |
| name | Lakefield + |
| process | 22 nm (0.022 μm, 2.2e-5 mm) + and 10 nm (0.01 μm, 1.0e-5 mm) + |