Difference between revisions of "intel/xeon silver/4209t"

	Edit Values
	Xeon Silver 4209T
	General Info
Designer	Intel
Manufacturer	Intel
Model Number	4209T
Part Number	CD8069503956900
S-Spec	SRFBQ; QPJM (QS)
Market	Server
Introduction	April 2, 2019 (announced); April 2, 2019 (launched)
Release Price	$501.00 (tray)
Shop	Amazon
	General Specs
Family	Xeon Silver
Series	4200
Locked	Yes
Frequency	2,200 MHz
Turbo Frequency	3,200 MHz (1 core)
Clock multiplier	22
	Microarchitecture
ISA	x86-64 (x86)
Microarchitecture	Cascade Lake
Platform	Purley
Chipset	Lewisburg
Core Name	Cascade Lake SP
Core Family	6
Core Stepping	R0, R1
Process	14 nm
Technology	CMOS
Word Size	64 bit
Cores	8
Threads	16
Max Memory	1 TiB
	Multiprocessing
Max SMP	2-Way (Multiprocessor)
Interconnect	UPI
Interconnect Links	2
Interconnect Rate	9.6 GT/s
	Electrical
TDP	70 W
Tcase	0 °C – 91 °C
	Packaging
Package	FCLGA-3647 (FCLGA)
Dimension	76.16 mm × 56.6 mm
Pitch	0.8585 mm × 0.9906 mm
Contacts	3647
Socket	Socket P, LGA-3647
	Succession
	Xeon Silver 4109T

Latest revision as of 11:16, 29 December 2019

Xeon Silver 4209T is a 64-bit octa-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4209T is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a turbo boost frequency of up to 3.2 GHz.

As indicated by the "T" suffix, this model has extended lifetime (10 year use) guarantees and NEBS-friendly packing specification.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

Cache Organization

Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.

L1$

512 KiB

524,288 B
0.5 MiB

L1I$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative
L1D$	256 KiB 262,144 B 0.25 MiB	8x32 KiB	8-way set associative	write-back

L2$

8 MiB

8,192 KiB
8,388,608 B
0.00781 GiB

		8x1 MiB	16-way set associative	write-back

L3$

11 MiB

11,264 KiB
11,534,336 B
0.0107 GiB

		8x1.375 MiB	11-way set associative	write-back

Memory controller[edit]

[Edit/Modify Memory Info]

Integrated Memory Controller

Max Type	DDR4-2400
Supports ECC	Yes
Max Mem	1 TiB
Controllers	2
Channels	6
Max Bandwidth	107.3 GiB/s 109,875.2 MiB/s 115.212 GB/s 115,212.498 MB/s 0.105 TiB/s 0.115 TB/s
Bandwidth	Single 17.88 GiB/s Double 35.76 GiB/s Quad 71.53 GiB/s Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

Expansion Options

PCIe	Revision: 3.0
	Max Lanes: 48
	Configuration: 1x16, x8, x4

Features[edit]

[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features

MMX	MMX Extension
EMMX	Extended MMX Extension
SSE	Streaming SIMD Extensions
SSE2	Streaming SIMD Extensions 2
SSE3	Streaming SIMD Extensions 3
SSSE3	Supplemental SSE3
SSE4.1	Streaming SIMD Extensions 4.1
SSE4.2	Streaming SIMD Extensions 4.2
AVX	Advanced Vector Extensions
AVX2	Advanced Vector Extensions 2
AVX-512	Advanced Vector 512-bit
AVX512F	AVX-512 Foundation
AVX512CD	AVX-512 Conflict Detection
AVX512BW	AVX-512 Byte and Word
AVX512DQ	AVX-512 Doubleword and Quadword Instructions
AVX512VL	AVX-512 Vector Length
AVX512_VNNI	AVX-512 Vector Neural Network Instructions
ABM	Advanced Bit Manipulation
BMI1	Bit Manipulation Instruction Set 1
BMI2	Bit Manipulation Instruction Set 2
FMA3	3-Operand Fused-Multiply-Add
AES	AES Encryption Instructions
RdRand	Hardware RNG
ADX	Multi-Precision Add-Carry
CLMUL	Carry-less Multiplication Extension
F16C	16-bit Floating Point Conversion

x86-16	16-bit x86
x86-32	32-bit x86
x86-64	64-bit x86
Real	Real Mode
Protected	Protected Mode
SMM	System Management Mode
FPU	Integrated x87 FPU
NX	No-eXecute
HT	Hyper-Threading
TBT 2.0	Turbo Boost Technology 2.0
EIST	Enhanced SpeedStep Technology
SST	Speed Shift Technology
TXT	Trusted Execution Technology (SMX)
vPro	Intel vPro
VT-x	VT-x (Virtualization)
VT-d	VT-d (I/O MMU virtualization)
EPT	Extended Page Tables (SLAT)
TSX	Transactional Synchronization Extensions
VMD	Volume Management Device
NM	Node Manager
KPT	Key Protection Technology
PTT	Platform Trust Technology
MBE Ctrl	Mode-Based Execute Control
DL Boost	Deep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

Mode	Base	Turbo Frequency/Active Cores
Mode	Base	1	2	3	4	5	6	7	8
Normal	2,200MHz	3,200MHz	3,200MHz	3,000MHz	3,000MHz	2,500MHz	2,500MHz	2,500MHz	2,500MHz
AVX2	2,100MHz	3,000MHz	3,000MHz	2,700MHz	2,700MHz	2,100MHz	2,100MHz	2,100MHz	2,100MHz
AVX512	1,200MHz	2,000MHz	2,000MHz	1,800MHz	1,800MHz	1,500MHz	1,500MHz	1,500MHz	1,500MHz

@@ Line 8: / Line 8: @@
 |part number=CD8069503956900
 |s-spec=SRFBQ
+|s-spec qs=QPJM
 |market=Server
 |first announced=April 2, 2019
@@ Line 25: / Line 26: @@
 |core name=Cascade Lake SP
 |core family=6
-|core stepping=R1
+|core stepping=R0
+|core stepping 2=R1
 |process=14 nm
 |technology=CMOS
@@ Line 31: / Line 33: @@
 |core count=8
 |thread count=16
+|max memory=1 TiB
 |max cpus=2
-|max memory=1 TiB
+|smp interconnect=UPI
+|smp interconnect links=2
+|smp interconnect rate=9.6 GT/s
 |tdp=70 W
 |tcase min=0 °C
 |tcase max=91 °C
 |package name 1=intel,fclga_3647
+|predecessor=Xeon Silver 4109T
+|predecessor link=intel/xeon silver/4109t
 }}
 '''Xeon Silver 4209T''' is a {{arch|64}} [[octa-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4209T is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz.

Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.	Xeon Silver 4209T - Intel#pcie +
base frequency	2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipset	Lewisburg +
clock multiplier	22 +
core count	8 +
core family	6 +
core name	Cascade Lake SP +
core stepping	R1 + and R0 +
designer	Intel +
family	Xeon Silver +
first announced	April 2, 2019 +
first launched	April 2, 2019 +
full page name	intel/xeon silver/4209t +
has advanced vector extensions	true +
has advanced vector extensions 2	true +
has advanced vector extensions 512	true +
has ecc memory support	true +
has extended page tables support	true +
has feature	Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost +
has intel deep learning boost	true +
has intel enhanced speedstep technology	true +
has intel speed shift technology	true +
has intel trusted execution technology	true +
has intel turbo boost technology 2 0	true +
has intel vpro technology	true +
has intel vt-d technology	true +
has intel vt-x technology	true +
has locked clock multiplier	true +
has second level address translation support	true +
has simultaneous multithreading	true +
has transactional synchronization extensions	true +
has x86 advanced encryption standard instruction set extension	true +
instance of	microprocessor +
isa	x86-64 +
isa family	x86 +
l1$ size	512 KiB (524,288 B, 0.5 MiB) +
l1d$ description	8-way set associative +
l1d$ size	256 KiB (262,144 B, 0.25 MiB) +
l1i$ description	8-way set associative +
l1i$ size	256 KiB (262,144 B, 0.25 MiB) +
l2$ description	16-way set associative +
l2$ size	8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description	11-way set associative +
l3$ size	11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldate	April 2, 2019 +
main image	+
manufacturer	Intel +
market segment	Server +
max case temperature	364.15 K (91 °C, 195.8 °F, 655.47 °R) +
max cpu count	2 +
max memory	1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) +
max memory bandwidth	107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels	6 +
microarchitecture	Cascade Lake +
min case temperature	273.15 K (0 °C, 32 °F, 491.67 °R) +
model number	4209T +
name	Xeon Silver 4209T +
package	FCLGA-3647 +
part number	CD8069503956900 +
platform	Purley +
process	14 nm (0.014 μm, 1.4e-5 mm) +
release price	$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
release price (tray)	$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
s-spec	SRFBQ +
s-spec (qs)	QPJM +
series	4200 +
smp interconnect	UPI +
smp interconnect links	2 +
smp interconnect rate	9.6 GT/s +
smp max ways	2 +
socket	Socket P + and LGA-3647 +
supported memory type	DDR4-2400 +
tdp	70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
technology	CMOS +
thread count	16 +
turbo frequency (1 core)	3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size	64 bit (8 octets, 16 nibbles) +

WikiChip

The Fuse Coverage

Social Media

Companies

Microarchitectures

Technology Nodes

Intel

AMD

ARM

Cavium

Samsung

Intel

AMD

Ampere

Apple

Cavium

HiSilicon

MediaTek

NXP

Qualcomm

Renesas