From WikiChip
Difference between revisions of "intel/xeon gold/6262v"
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|manufacturer=Intel | |manufacturer=Intel | ||
|model number=6262V | |model number=6262V | ||
+ | |s-spec qs=QS2B | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
Line 27: | Line 28: | ||
|core family=6 | |core family=6 | ||
|core model=85 | |core model=85 | ||
+ | |core stepping=B1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 32: | Line 34: | ||
|core count=24 | |core count=24 | ||
|thread count=48 | |thread count=48 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=135 W | |tdp=135 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
Line 39: | Line 44: | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Gold 6262V''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6262V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4- | + | '''Xeon Gold 6262V''' is a {{arch|64}} [[24-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6262V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.9 GHz with a TDP of 135 W and features a {{intel|turbo boost}} frequency of up to 3.6 GHz. |
Line 191: | Line 196: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=1,900MHz | ||
+ | |freq_1=3,600MHz | ||
+ | |freq_2=3,600MHz | ||
+ | |freq_3=3,400MHz | ||
+ | |freq_4=3,400MHz | ||
+ | |freq_5=3,300MHz | ||
+ | |freq_6=3,300MHz | ||
+ | |freq_7=3,300MHz | ||
+ | |freq_8=3,300MHz | ||
+ | |freq_9=3,200MHz | ||
+ | |freq_10=3,200MHz | ||
+ | |freq_11=3,200MHz | ||
+ | |freq_12=3,200MHz | ||
+ | |freq_13=2,900MHz | ||
+ | |freq_14=2,900MHz | ||
+ | |freq_15=2,900MHz | ||
+ | |freq_16=2,900MHz | ||
+ | |freq_17=2,600MHz | ||
+ | |freq_18=2,600MHz | ||
+ | |freq_19=2,600MHz | ||
+ | |freq_20=2,600MHz | ||
+ | |freq_21=2,500MHz | ||
+ | |freq_22=2,500MHz | ||
+ | |freq_23=2,500MHz | ||
+ | |freq_24=2,500MHz | ||
+ | |freq_avx2_base=1,600MHz | ||
+ | |freq_avx2_1=3,800MHz | ||
+ | |freq_avx2_2=3,800MHz | ||
+ | |freq_avx2_3=3,600MHz | ||
+ | |freq_avx2_4=3,600MHz | ||
+ | |freq_avx2_5=3,500MHz | ||
+ | |freq_avx2_6=3,500MHz | ||
+ | |freq_avx2_7=3,500MHz | ||
+ | |freq_avx2_8=3,500MHz | ||
+ | |freq_avx2_9=3,400MHz | ||
+ | |freq_avx2_10=3,400MHz | ||
+ | |freq_avx2_11=3,400MHz | ||
+ | |freq_avx2_12=3,400MHz | ||
+ | |freq_avx2_13=3,000MHz | ||
+ | |freq_avx2_14=3,000MHz | ||
+ | |freq_avx2_15=3,000MHz | ||
+ | |freq_avx2_16=3,000MHz | ||
+ | |freq_avx2_17=2,800MHz | ||
+ | |freq_avx2_18=2,800MHz | ||
+ | |freq_avx2_19=2,800MHz | ||
+ | |freq_avx2_20=2,800MHz | ||
+ | |freq_avx512_base=1,100MHz | ||
+ | |freq_avx512_1=3,200MHz | ||
+ | |freq_avx512_2=3,200MHz | ||
+ | |freq_avx512_3=3,000MHz | ||
+ | |freq_avx512_4=3,000MHz | ||
+ | |freq_avx512_5=2,800MHz | ||
+ | |freq_avx512_6=2,800MHz | ||
+ | |freq_avx512_7=2,800MHz | ||
+ | |freq_avx512_8=2,800MHz | ||
+ | |freq_avx512_9=2,400MHz | ||
+ | |freq_avx512_10=2,400MHz | ||
+ | |freq_avx512_11=2,400MHz | ||
+ | |freq_avx512_12=2,400MHz | ||
+ | |freq_avx512_13=2,200MHz | ||
+ | |freq_avx512_14=2,200MHz | ||
+ | |freq_avx512_15=2,200MHz | ||
+ | |freq_avx512_16=2,200MHz | ||
+ | |freq_avx512_17=2,000MHz | ||
+ | |freq_avx512_18=2,000MHz | ||
+ | |freq_avx512_19=2,000MHz | ||
+ | |freq_avx512_20=2,000MHz | ||
+ | |freq_avx512_21=1,900MHz | ||
+ | |freq_avx512_22=1,900MHz | ||
+ | |freq_avx512_23=1,900MHz | ||
+ | |freq_avx512_24=1,900MHz | ||
}} | }} |
Latest revision as of 01:18, 29 December 2019
Edit Values | |
Xeon Gold 6262V | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6262V |
S-Spec | QS2B (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $2,900.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 1,900 MHz |
Turbo Frequency | 3,600 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 19 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | B1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 24 |
Threads | 48 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 135 W |
Tcase | 0 °C – 91 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6262V is a 64-bit 24-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6262V is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.9 GHz with a TDP of 135 W and features a turbo boost frequency of up to 3.6 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | ||
Normal | 1,900MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,200MHz | 3,200MHz | 3,200MHz | 3,200MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz |
AVX2 | 1,600MHz | 3,800MHz | 3,800MHz | 3,600MHz | 3,600MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | ||||
AVX512 | 1,100MHz | 3,200MHz | 3,200MHz | 3,000MHz | 3,000MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,000MHz | 2,000MHz | 2,000MHz | 2,000MHz | 1,900MHz | 1,900MHz | 1,900MHz | 1,900MHz |
Facts about "Xeon Gold 6262V - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6262V - Intel#pcie + |
base frequency | 1,900 MHz (1.9 GHz, 1,900,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 19 + |
core count | 24 + |
core family | 6 + |
core model | 85 + |
core name | Cascade Lake SP + |
core stepping | B1 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/6262v + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,536 KiB (1,572,864 B, 1.5 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 768 KiB (786,432 B, 0.75 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 24 MiB (24,576 KiB, 25,165,824 B, 0.0234 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 33 MiB (33,792 KiB, 34,603,008 B, 0.0322 GiB) + |
ldate | April 2, 2019 + |
main image | + |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 364.15 K (91 °C, 195.8 °F, 655.47 °R) + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 6262V + |
name | Xeon Gold 6262V + |
package | FCLGA-3647 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 2,900.00 (€ 2,610.00, £ 2,349.00, ¥ 299,657.00) + |
release price (tray) | $ 2,900.00 (€ 2,610.00, £ 2,349.00, ¥ 299,657.00) + |
s-spec (qs) | QS2B + |
series | 6200 + |
smp interconnect | UPI + |
smp interconnect links | 3 + |
smp interconnect rate | 10.4 GT/s + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 135 W (135,000 mW, 0.181 hp, 0.135 kW) + |
technology | CMOS + |
thread count | 48 + |
turbo frequency (1 core) | 3,600 MHz (3.6 GHz, 3,600,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |