From WikiChip
Difference between revisions of "intel/xeon gold/6222v"
(3 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{intel title|Xeon Gold 6222V}} | {{intel title|Xeon Gold 6222V}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Xeon Gold 6222V | ||
+ | |image=cascade lake sp (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=6222V | ||
+ | |s-spec qs=QS2C | ||
+ | |market=Server | ||
+ | |first announced=April 2, 2019 | ||
+ | |first launched=April 2, 2019 | ||
+ | |release price (tray)=$1,600.00 | ||
+ | |family=Xeon Gold | ||
+ | |series=6200 | ||
+ | |locked=Yes | ||
+ | |frequency=1,800 MHz | ||
+ | |turbo frequency1=3,600 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=18 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Cascade Lake | ||
+ | |platform=Purley | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Cascade Lake SP | ||
+ | |core family=6 | ||
+ | |core model=85 | ||
+ | |core stepping=H0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |word size=64 bit | ||
+ | |core count=20 | ||
+ | |thread count=40 | ||
+ | |max memory=1 TiB | ||
+ | |max cpus=4 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
+ | |tdp=115 W | ||
+ | |tcase min=0 °C | ||
+ | |tcase max=83 °C | ||
+ | |package name 1=intel,fclga_3647 | ||
+ | }} | ||
'''Xeon Gold 6222V''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6222V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.8 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.6 GHz. | '''Xeon Gold 6222V''' is a {{arch|64}} [[20-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 6222V is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports 2 {{x86|AVX-512}} [[FMA]] units as well as three {{intel|Ultra Path Interconnect}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.8 GHz with a TDP of 115 W and features a {{intel|turbo boost}} frequency of up to 3.6 GHz. | ||
Line 113: | Line 156: | ||
|kpt=Yes | |kpt=Yes | ||
|ptt=Yes | |ptt=Yes | ||
− | |intelrunsure= | + | |intelrunsure=Yes |
|mbe=Yes | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
Line 152: | Line 195: | ||
|amdpb2=No | |amdpb2=No | ||
|amdpbod=No | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=1,800MHz | ||
+ | |freq_1=3,600MHz | ||
+ | |freq_2=3,600MHz | ||
+ | |freq_3=3,400MHz | ||
+ | |freq_4=3,400MHz | ||
+ | |freq_5=3,300MHz | ||
+ | |freq_6=3,300MHz | ||
+ | |freq_7=3,300MHz | ||
+ | |freq_8=3,300MHz | ||
+ | |freq_9=2,900MHz | ||
+ | |freq_10=2,900MHz | ||
+ | |freq_11=2,900MHz | ||
+ | |freq_12=2,900MHz | ||
+ | |freq_13=2,600MHz | ||
+ | |freq_14=2,600MHz | ||
+ | |freq_15=2,600MHz | ||
+ | |freq_16=2,600MHz | ||
+ | |freq_17=2,400MHz | ||
+ | |freq_18=2,400MHz | ||
+ | |freq_19=2,400MHz | ||
+ | |freq_20=2,400MHz | ||
+ | |freq_avx2_base=1,600MHz | ||
+ | |freq_avx2_1=3,300MHz | ||
+ | |freq_avx2_2=3,300MHz | ||
+ | |freq_avx2_3=3,100MHz | ||
+ | |freq_avx2_4=3,100MHz | ||
+ | |freq_avx2_5=3,000MHz | ||
+ | |freq_avx2_6=3,000MHz | ||
+ | |freq_avx2_7=3,000MHz | ||
+ | |freq_avx2_8=3,000MHz | ||
+ | |freq_avx2_9=2,600MHz | ||
+ | |freq_avx2_10=2,600MHz | ||
+ | |freq_avx2_11=2,600MHz | ||
+ | |freq_avx2_12=2,600MHz | ||
+ | |freq_avx2_13=2,300MHz | ||
+ | |freq_avx2_14=2,300MHz | ||
+ | |freq_avx2_15=2,300MHz | ||
+ | |freq_avx2_16=2,300MHz | ||
+ | |freq_avx2_17=2,200MHz | ||
+ | |freq_avx2_18=2,200MHz | ||
+ | |freq_avx2_19=2,200MHz | ||
+ | |freq_avx2_20=2,200MHz | ||
+ | |freq_avx512_base=1,100MHz | ||
+ | |freq_avx512_1=3,000MHz | ||
+ | |freq_avx512_2=3,000MHz | ||
+ | |freq_avx512_3=2,800MHz | ||
+ | |freq_avx512_4=2,800MHz | ||
+ | |freq_avx512_5=2,500MHz | ||
+ | |freq_avx512_6=2,500MHz | ||
+ | |freq_avx512_7=2,500MHz | ||
+ | |freq_avx512_8=2,500MHz | ||
+ | |freq_avx512_9=2,100MHz | ||
+ | |freq_avx512_10=2,100MHz | ||
+ | |freq_avx512_11=2,100MHz | ||
+ | |freq_avx512_12=2,100MHz | ||
+ | |freq_avx512_13=1,900MHz | ||
+ | |freq_avx512_14=1,900MHz | ||
+ | |freq_avx512_15=1,900MHz | ||
+ | |freq_avx512_16=1,900MHz | ||
+ | |freq_avx512_17=1,800MHz | ||
+ | |freq_avx512_18=1,800MHz | ||
+ | |freq_avx512_19=1,800MHz | ||
+ | |freq_avx512_20=1,800MHz | ||
}} | }} |
Latest revision as of 01:57, 29 December 2019
Edit Values | |
Xeon Gold 6222V | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 6222V |
S-Spec | QS2C (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $1,600.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 6200 |
Locked | Yes |
Frequency | 1,800 MHz |
Turbo Frequency | 3,600 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 18 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Model | 85 |
Core Stepping | H0 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 20 |
Threads | 40 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 115 W |
Tcase | 0 °C – 83 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 6222V is a 64-bit 20-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 6222V is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports 2 AVX-512 FMA units as well as three Ultra Path Interconnect links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 1.8 GHz with a TDP of 115 W and features a turbo boost frequency of up to 3.6 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
||||||||||||||||||||||||||||||||||||
|
Memory controller[edit]
![]() |
Integrated Memory Controller
|
|||||||||||||
|
Expansions[edit]
![]() |
Expansion Options |
||||
|
Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | ||
Normal | 1,800MHz | 3,600MHz | 3,600MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,400MHz | 2,400MHz | 2,400MHz | 2,400MHz |
AVX2 | 1,600MHz | 3,300MHz | 3,300MHz | 3,100MHz | 3,100MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,300MHz | 2,300MHz | 2,300MHz | 2,300MHz | 2,200MHz | 2,200MHz | 2,200MHz | 2,200MHz |
AVX512 | 1,100MHz | 3,000MHz | 3,000MHz | 2,800MHz | 2,800MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,100MHz | 2,100MHz | 2,100MHz | 2,100MHz | 1,900MHz | 1,900MHz | 1,900MHz | 1,900MHz | 1,800MHz | 1,800MHz | 1,800MHz | 1,800MHz |
Facts about "Xeon Gold 6222V - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Gold 6222V - Intel#pcie + |
full page name | intel/xeon gold/6222v + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
l1$ size | 1,280 KiB (1,310,720 B, 1.25 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 20 MiB (20,480 KiB, 20,971,520 B, 0.0195 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 27.5 MiB (28,160 KiB, 28,835,840 B, 0.0269 GiB) + |
ldate | 1900 + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
supported memory type | DDR4-2400 + |