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Difference between revisions of "intel/core i5/i5-9500f"
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{{intel title|Core i5-9500F}} | {{intel title|Core i5-9500F}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Core i5-9500F | ||
+ | |image=coffee lake s (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=i5-9500F | ||
+ | |part number=CM8068403362616 | ||
+ | |part number 2=CM8068403875414 | ||
+ | |s-spec=SRF6Q | ||
+ | |s-spec 2=SRG10 | ||
+ | |market=Desktop | ||
+ | |first announced=April 23, 2019 | ||
+ | |first launched=April 23, 2019 | ||
+ | |release price (tray)=$192.00 | ||
+ | |release price (box)=$202.00 | ||
+ | |family=Core i5 | ||
+ | |series=i5-9000 | ||
+ | |locked=Yes | ||
+ | |frequency=3,000 MHz | ||
+ | |turbo frequency1=4,400 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=30 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Coffee Lake | ||
+ | |platform=Coffee Lake | ||
+ | |chipset=Cannon Point | ||
+ | |core name=Coffee Lake R | ||
+ | |core family=6 | ||
+ | |core model=158 | ||
+ | |core stepping=U0 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |die area=149 mm² | ||
+ | |word size=64 bit | ||
+ | |core count=6 | ||
+ | |thread count=6 | ||
+ | |max cpus=1 | ||
+ | |max memory=128 GiB | ||
+ | |tdp=65 W | ||
+ | |tjunc min=0 °C | ||
+ | |tjunc max=100 °C | ||
+ | |package module 1={{packages/intel/lga-1151}} | ||
+ | }} | ||
'''Core i5-9500F''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2019]]. This processor, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is manufactured on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]]. The i5-9500F operates at a 3 GHz with a TDP of 65 W and a {{intel|Turbo Boost}} frequency of up to 4.4 GHz. This chip supports up to 128 GiB of dual-channel DDR4-2666 memory. | '''Core i5-9500F''' is a {{arch|64}} [[hexa-core]] mid-range performance [[x86]] desktop microprocessor introduced by [[Intel]] in early [[2019]]. This processor, which is based on the {{intel|Coffee Lake|l=arch}} microarchitecture, is manufactured on Intel's 3rd generation enhanced [[14 nm process|14nm++ process]]. The i5-9500F operates at a 3 GHz with a TDP of 65 W and a {{intel|Turbo Boost}} frequency of up to 4.4 GHz. This chip supports up to 128 GiB of dual-channel DDR4-2666 memory. | ||
This is model is identical to the {{\\|i5-9500}} except it comes without integrated graphics. | This is model is identical to the {{\\|i5-9500}} except it comes without integrated graphics. | ||
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/coffee_lake#Memory_Hierarchy|l1=Coffee Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=384 KiB | ||
+ | |l1i cache=192 KiB | ||
+ | |l1i break=6x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=192 KiB | ||
+ | |l1d break=6x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=1.5 MiB | ||
+ | |l2 break=6x256 KiB | ||
+ | |l2 desc=4-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=9 MiB | ||
+ | |l3 break=6x1.5 MiB | ||
+ | |l3 desc=12-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=No | ||
+ | |max mem=128 GiB | ||
+ | |controllers=1 | ||
+ | |channels=2 | ||
+ | |max bandwidth=39.74 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=16 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=2x8 | ||
+ | |pcie config 3=1x8+2x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Graphics == | ||
+ | This processor has no integrated graphics. | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=No | ||
+ | |avx512cd=No | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=No | ||
+ | |avx512dq=No | ||
+ | |avx512vl=No | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=No | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=No | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=No | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=No | ||
+ | |kpt=No | ||
+ | |ptt=No | ||
+ | |intelrunsure=No | ||
+ | |mbe=No | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=No | ||
+ | |ht=No | ||
+ | |vpro=No | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=No | ||
+ | |dlboost=No | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} |
Latest revision as of 00:52, 7 May 2019
Edit Values | ||||||||||||
Core i5-9500F | ||||||||||||
General Info | ||||||||||||
Designer | Intel | |||||||||||
Manufacturer | Intel | |||||||||||
Model Number | i5-9500F | |||||||||||
Part Number | CM8068403362616, CM8068403875414 | |||||||||||
S-Spec | SRF6Q, SRG10 | |||||||||||
Market | Desktop | |||||||||||
Introduction | April 23, 2019 (announced) April 23, 2019 (launched) | |||||||||||
Release Price | $192.00 (tray) $202.00 (box) | |||||||||||
Shop | Amazon | |||||||||||
General Specs | ||||||||||||
Family | Core i5 | |||||||||||
Series | i5-9000 | |||||||||||
Locked | Yes | |||||||||||
Frequency | 3,000 MHz | |||||||||||
Turbo Frequency | 4,400 MHz (1 core) | |||||||||||
Bus type | DMI 3.0 | |||||||||||
Bus rate | 4 × 8 GT/s | |||||||||||
Clock multiplier | 30 | |||||||||||
Microarchitecture | ||||||||||||
ISA | x86-64 (x86) | |||||||||||
Microarchitecture | Coffee Lake | |||||||||||
Platform | Coffee Lake | |||||||||||
Chipset | Cannon Point | |||||||||||
Core Name | Coffee Lake R | |||||||||||
Core Family | 6 | |||||||||||
Core Model | 158 | |||||||||||
Core Stepping | U0 | |||||||||||
Process | 14 nm | |||||||||||
Technology | CMOS | |||||||||||
Die | 149 mm² | |||||||||||
Word Size | 64 bit | |||||||||||
Cores | 6 | |||||||||||
Threads | 6 | |||||||||||
Max Memory | 128 GiB | |||||||||||
Multiprocessing | ||||||||||||
Max SMP | 1-Way (Uniprocessor) | |||||||||||
Electrical | ||||||||||||
TDP | 65 W | |||||||||||
Tjunction | 0 °C – 100 °C | |||||||||||
Packaging | ||||||||||||
|
Core i5-9500F is a 64-bit hexa-core mid-range performance x86 desktop microprocessor introduced by Intel in early 2019. This processor, which is based on the Coffee Lake microarchitecture, is manufactured on Intel's 3rd generation enhanced 14nm++ process. The i5-9500F operates at a 3 GHz with a TDP of 65 W and a Turbo Boost frequency of up to 4.4 GHz. This chip supports up to 128 GiB of dual-channel DDR4-2666 memory.
This is model is identical to the i5-9500 except it comes without integrated graphics.
Cache[edit]
- Main article: Coffee Lake § Cache
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
Integrated Memory Controller
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Expansions[edit]
Expansion Options |
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Graphics[edit]
This processor has no integrated graphics.
Features[edit]
[Edit/Modify Supported Features]
Facts about "Core i5-9500F - Intel"
full page name | intel/core i5/i5-9500f + |
instance of | microprocessor + |
ldate | 1900 + |