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Difference between revisions of "intel/xeon gold/5218n"
(7 intermediate revisions by the same user not shown) | |||
Line 8: | Line 8: | ||
|part number=CD8069504289900 | |part number=CD8069504289900 | ||
|s-spec=SRFD9 | |s-spec=SRFD9 | ||
+ | |s-spec qs=QRGD | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
Line 16: | Line 17: | ||
|locked=Yes | |locked=Yes | ||
|frequency=2,300 MHz | |frequency=2,300 MHz | ||
+ | |turbo frequency1=3,700 MHz | ||
|bus type=DMI 3.0 | |bus type=DMI 3.0 | ||
|bus links=4 | |bus links=4 | ||
Line 28: | Line 30: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
− | |core stepping=L1 | + | |core stepping=L0 |
+ | |core stepping 2=L1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 34: | Line 37: | ||
|core count=16 | |core count=16 | ||
|thread count=32 | |thread count=32 | ||
+ | |max memory=1 TiB | ||
|max cpus=4 | |max cpus=4 | ||
− | | | + | |smp interconnect=UPI |
+ | |smp interconnect links=3 | ||
+ | |smp interconnect rate=10.4 GT/s | ||
|tdp=105 W | |tdp=105 W | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
}} | }} | ||
− | '''Xeon Gold 5218N''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5218N is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as | + | '''Xeon Gold 5218N''' is a {{arch|64}} [[16-core]] [[x86]] high performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Gold 5218N is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports 4-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 105 W and features a {{intel|turbo boost}} frequency of up to 3.7 GHz. |
+ | |||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=1 MiB | ||
+ | |l1i cache=512 KiB | ||
+ | |l1i break=16x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=512 KiB | ||
+ | |l1d break=16x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=16 MiB | ||
+ | |l2 break=16x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=22 MiB | ||
+ | |l3 break=16x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2666 | ||
+ | |ecc=Yes | ||
+ | |max mem=1 TiB | ||
+ | |controllers=2 | ||
+ | |channels=6 | ||
+ | |max bandwidth=119.21 GiB/s | ||
+ | |bandwidth schan=19.87 GiB/s | ||
+ | |bandwidth dchan=39.74 GiB/s | ||
+ | |bandwidth qchan=79.47 GiB/s | ||
+ | |bandwidth hchan=119.21 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=48 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=No | ||
+ | |avx=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=No | ||
+ | |avx512pf=No | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=No | ||
+ | |avx512vbmi=No | ||
+ | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=No | ||
+ | |avx512vpopcntdq=No | ||
+ | |abm=Yes | ||
+ | |tbm=No | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=No | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=No | ||
+ | |xop=No | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=No | ||
+ | |tbt1=No | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=No | ||
+ | |bpt=No | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=No | ||
+ | |fastmem=No | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=No | ||
+ | |mbe=Yes | ||
+ | |isrt=No | ||
+ | |sba=No | ||
+ | |mwt=No | ||
+ | |sipp=No | ||
+ | |att=No | ||
+ | |ipt=No | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=No | ||
+ | |sgx=No | ||
+ | |securekey=No | ||
+ | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
+ | |3dnow=No | ||
+ | |e3dnow=No | ||
+ | |smartmp=No | ||
+ | |powernow=No | ||
+ | |amdvi=No | ||
+ | |amdv=No | ||
+ | |amdsme=No | ||
+ | |amdtsme=No | ||
+ | |amdsev=No | ||
+ | |rvi=No | ||
+ | |smt=No | ||
+ | |sensemi=No | ||
+ | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,300MHz | ||
+ | |freq_1=3,700MHz | ||
+ | |freq_2=3,700MHz | ||
+ | |freq_3=3,500MHz | ||
+ | |freq_4=3,500MHz | ||
+ | |freq_5=3,400MHz | ||
+ | |freq_6=3,400MHz | ||
+ | |freq_7=3,400MHz | ||
+ | |freq_8=3,400MHz | ||
+ | |freq_9=3,300MHz | ||
+ | |freq_10=3,300MHz | ||
+ | |freq_11=3,300MHz | ||
+ | |freq_12=3,300MHz | ||
+ | |freq_13=3,000MHz | ||
+ | |freq_14=3,000MHz | ||
+ | |freq_15=3,000MHz | ||
+ | |freq_16=3,000MHz | ||
+ | |freq_avx2_base=1,600MHz | ||
+ | |freq_avx2_1=2,900MHz | ||
+ | |freq_avx2_2=2,900MHz | ||
+ | |freq_avx2_3=2,800MHz | ||
+ | |freq_avx2_4=2,800MHz | ||
+ | |freq_avx2_5=2,800MHz | ||
+ | |freq_avx2_6=2,800MHz | ||
+ | |freq_avx2_7=2,800MHz | ||
+ | |freq_avx2_8=2,800MHz | ||
+ | |freq_avx2_9=2,800MHz | ||
+ | |freq_avx2_10=2,800MHz | ||
+ | |freq_avx2_11=2,800MHz | ||
+ | |freq_avx2_12=2,800MHz | ||
+ | |freq_avx2_13=2,800MHz | ||
+ | |freq_avx2_14=2,800MHz | ||
+ | |freq_avx2_15=2,800MHz | ||
+ | |freq_avx2_16=2,800MHz | ||
+ | |freq_avx512_base=1,200MHz | ||
+ | |freq_avx512_1=2,900MHz | ||
+ | |freq_avx512_2=2,900MHz | ||
+ | |freq_avx512_3=2,700MHz | ||
+ | |freq_avx512_4=2,700MHz | ||
+ | |freq_avx512_5=2,600MHz | ||
+ | |freq_avx512_6=2,600MHz | ||
+ | |freq_avx512_7=2,600MHz | ||
+ | |freq_avx512_8=2,600MHz | ||
+ | |freq_avx512_9=2,600MHz | ||
+ | |freq_avx512_10=2,600MHz | ||
+ | |freq_avx512_11=2,600MHz | ||
+ | |freq_avx512_12=2,600MHz | ||
+ | |freq_avx512_13=2,500MHz | ||
+ | |freq_avx512_14=2,500MHz | ||
+ | |freq_avx512_15=2,500MHz | ||
+ | |freq_avx512_16=2,500MHz | ||
+ | }} |
Latest revision as of 00:22, 29 December 2019
Edit Values | |
Xeon Gold 5218N | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 5218N |
Part Number | CD8069504289900 |
S-Spec | SRFD9 QRGD (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $1,375.00 (tray) |
Shop | Amazon |
General Specs | |
Family | Xeon Gold |
Series | 5200 |
Locked | Yes |
Frequency | 2,300 MHz |
Turbo Frequency | 3,700 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 23 |
CPUID | 0x50655 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | L0, L1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 16 |
Threads | 32 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 4-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 3 |
Interconnect Rate | 10.4 GT/s |
Electrical | |
TDP | 105 W |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Xeon Gold 5218N is a 64-bit 16-core x86 high performance server microprocessor introduced by Intel in early 2019. The Gold 5218N is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports 4-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2666 memory, operates at 2.3 GHz with a TDP of 105 W and features a turbo boost frequency of up to 3.7 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
![]() |
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
![]() |
Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | ||
Normal | 2,300MHz | 3,700MHz | 3,700MHz | 3,500MHz | 3,500MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,400MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,300MHz | 3,000MHz | 3,000MHz | 3,000MHz | 3,000MHz |
AVX2 | 1,600MHz | 2,900MHz | 2,900MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz | 2,800MHz |
AVX512 | 1,200MHz | 2,900MHz | 2,900MHz | 2,700MHz | 2,700MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,600MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz |
Facts about "Xeon Gold 5218N - Intel"
base frequency | 2,300 MHz (2.3 GHz, 2,300,000 kHz) + |
bus links | 4 + |
bus rate | 8,000 MT/s (8 GT/s, 8,000,000 kT/s) + |
bus type | DMI 3.0 + |
chipset | Lewisburg + |
clock multiplier | 23 + |
core count | 16 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | L1 + |
cpuid | 0x50655 + |
designer | Intel + |
family | Xeon Gold + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon gold/5218n + |
has locked clock multiplier | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 1,024 KiB (1,048,576 B, 1 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 512 KiB (524,288 B, 0.5 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 22 MiB (22,528 KiB, 23,068,672 B, 0.0215 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max cpu count | 4 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
microarchitecture | Cascade Lake + |
model number | 5218N + |
name | Xeon Gold 5218N + |
package | FCLGA-3647 + |
part number | CD8069504289900 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) + |
release price (tray) | $ 1,375.00 (€ 1,237.50, £ 1,113.75, ¥ 142,078.75) + |
s-spec | SRFD9 + |
series | 5200 + |
smp max ways | 4 + |
socket | Socket P + and LGA-3647 + |
tdp | 105 W (105,000 mW, 0.141 hp, 0.105 kW) + |
technology | CMOS + |
thread count | 32 + |
word size | 64 bit (8 octets, 16 nibbles) + |