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Difference between revisions of "intel/xeon silver/4209t"
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|part number=CD8069503956900
 
|part number=CD8069503956900
 
|s-spec=SRFBQ
 
|s-spec=SRFBQ
 +
|s-spec qs=QPJM
 
|market=Server
 
|market=Server
 
|first announced=April 2, 2019
 
|first announced=April 2, 2019
Line 25: Line 26:
 
|core name=Cascade Lake SP
 
|core name=Cascade Lake SP
 
|core family=6
 
|core family=6
−
|core stepping=R1
+
|core stepping=R0
 +
|core stepping 2=R1
 
|process=14 nm
 
|process=14 nm
 
|technology=CMOS
 
|technology=CMOS
Line 31: Line 33:
 
|core count=8
 
|core count=8
 
|thread count=16
 
|thread count=16
 +
|max memory=1 TiB
 
|max cpus=2
 
|max cpus=2
 +
|smp interconnect=UPI
 +
|smp interconnect links=2
 +
|smp interconnect rate=9.6 GT/s
 
|tdp=70 W
 
|tdp=70 W
 
|tcase min=0 °C
 
|tcase min=0 °C
 
|tcase max=91 °C
 
|tcase max=91 °C
 
|package name 1=intel,fclga_3647
 
|package name 1=intel,fclga_3647
 +
|predecessor=Xeon Silver 4109T
 +
|predecessor link=intel/xeon silver/4109t
 
}}
 
}}
 
'''Xeon Silver 4209T''' is a {{arch|64}} [[octa-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4209T is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz.
 
'''Xeon Silver 4209T''' is a {{arch|64}} [[octa-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4209T is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz.
 +
 +
As indicated by the "''T''" suffix, this model has extended lifetime (10 year use) guarantees and NEBS-friendly packing specification.
  
  
Line 81: Line 91:
 
|type=PCIe
 
|type=PCIe
 
|pcie revision=3.0
 
|pcie revision=3.0
−
|pcie lanes=40
+
|pcie lanes=48
 
|pcie config=1x16
 
|pcie config=1x16
 
|pcie config 2=x8
 
|pcie config 2=x8
 
|pcie config 3=x4
 
|pcie config 3=x4
 
}}
 
}}
 +
}}
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|bfloat16=No
 +
|tbt1=No
 +
|tbt2=Yes
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=Yes
 +
|sst=Yes
 +
|flex=No
 +
|fastmem=No
 +
|ivmd=Yes
 +
|intelnodecontroller=No
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=No
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=Yes
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}
 +
 +
== Frequencies ==
 +
{{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}}
 +
{{frequency table
 +
|freq_base=2,200MHz
 +
|freq_1=3,200MHz
 +
|freq_2=3,200MHz
 +
|freq_3=3,000MHz
 +
|freq_4=3,000MHz
 +
|freq_5=2,500MHz
 +
|freq_6=2,500MHz
 +
|freq_7=2,500MHz
 +
|freq_8=2,500MHz
 +
|freq_avx2_base=2,100MHz
 +
|freq_avx2_1=3,000MHz
 +
|freq_avx2_2=3,000MHz
 +
|freq_avx2_3=2,700MHz
 +
|freq_avx2_4=2,700MHz
 +
|freq_avx2_5=2,100MHz
 +
|freq_avx2_6=2,100MHz
 +
|freq_avx2_7=2,100MHz
 +
|freq_avx2_8=2,100MHz
 +
|freq_avx512_base=1,200MHz
 +
|freq_avx512_1=2,000MHz
 +
|freq_avx512_2=2,000MHz
 +
|freq_avx512_3=1,800MHz
 +
|freq_avx512_4=1,800MHz
 +
|freq_avx512_5=1,500MHz
 +
|freq_avx512_6=1,500MHz
 +
|freq_avx512_7=1,500MHz
 +
|freq_avx512_8=1,500MHz
 
}}
 
}}

Latest revision as of 11:16, 29 December 2019

Edit Values
Xeon Silver 4209T
cascade lake sp (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number4209T
Part NumberCD8069503956900
S-SpecSRFBQ
QPJM (QS)
MarketServer
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
Release Price$501.00 (tray)
ShopAmazon
General Specs
FamilyXeon Silver
Series4200
LockedYes
Frequency2,200 MHz
Turbo Frequency3,200 MHz (1 core)
Clock multiplier22
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformPurley
ChipsetLewisburg
Core NameCascade Lake SP
Core Family6
Core SteppingR0, R1
Process14 nm
TechnologyCMOS
Word Size64 bit
Cores8
Threads16
Max Memory1 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
InterconnectUPI
Interconnect Links2
Interconnect Rate9.6 GT/s
Electrical
TDP70 W
Tcase0 °C – 91 °C
Packaging
PackageFCLGA-3647 (FCLGA)
Dimension76.16 mm × 56.6 mm
Pitch0.8585 mm × 0.9906 mm
Contacts3647
SocketSocket P, LGA-3647
Succession

Xeon Silver 4209T is a 64-bit octa-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4209T is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 70 W and features a turbo boost frequency of up to 3.2 GHz.

As indicated by the "T" suffix, this model has extended lifetime (10 year use) guarantees and NEBS-friendly packing specification.


Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
524,288 B
0.5 MiB
L1I$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back
L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  8x1 MiB16-way set associativewrite-back
L3$11 MiB
11,264 KiB
11,534,336 B
0.0107 GiB
  8x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2400
Supports ECCYes
Max Mem1 TiB
Controllers2
Channels6
Max Bandwidth107.3 GiB/s
109,875.2 MiB/s
115.212 GB/s
115,212.498 MB/s
0.105 TiB/s
0.115 TB/s
Bandwidth
Single 17.88 GiB/s
Double 35.76 GiB/s
Quad 71.53 GiB/s
Hexa 107.3 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 48
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
MBE CtrlMode-Based Execute Control
DL BoostDeep Learning Boost

Frequencies[edit]

See also: Intel's CPU Frequency Behavior

[Modify Frequency Info]

ModeBaseTurbo Frequency/Active Cores
12345678
Normal2,200MHz3,200MHz3,200MHz3,000MHz3,000MHz2,500MHz2,500MHz2,500MHz2,500MHz
AVX22,100MHz3,000MHz3,000MHz2,700MHz2,700MHz2,100MHz2,100MHz2,100MHz2,100MHz
AVX5121,200MHz2,000MHz2,000MHz1,800MHz1,800MHz1,500MHz1,500MHz1,500MHz1,500MHz
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_silver/4209t&oldid=95207"
Facts about "Xeon Silver 4209T - Intel"
RDF feed
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Xeon Silver 4209T - Intel#pcie +
base frequency2,200 MHz (2.2 GHz, 2,200,000 kHz) +
chipsetLewisburg +
clock multiplier22 +
core count8 +
core family6 +
core nameCascade Lake SP +
core steppingR1 +
designerIntel +
familyXeon Silver +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon silver/4209t +
has ecc memory supporttrue +
has locked clock multipliertrue +
instance ofmicroprocessor +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description16-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description11-way set associative +
l3$ size11 MiB (11,264 KiB, 11,534,336 B, 0.0107 GiB) +
ldateApril 2, 2019 +
main imageFile:cascade lake sp (front).png +
manufacturerIntel +
market segmentServer +
max case temperature364.15 K (91 °C, 195.8 °F, 655.47 °R) +
max cpu count2 +
max memory bandwidth107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) +
max memory channels6 +
microarchitectureCascade Lake +
min case temperature273.15 K (0 °C, 32 °F, 491.67 °R) +
model number4209T +
nameXeon Silver 4209T +
packageFCLGA-3647 +
part numberCD8069503956900 +
platformPurley +
process14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
release price (tray)$ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) +
s-specSRFBQ +
series4200 +
smp max ways2 +
socketSocket P + and LGA-3647 +
supported memory typeDDR4-2400 +
tdp70 W (70,000 mW, 0.0939 hp, 0.07 kW) +
technologyCMOS +
thread count16 +
turbo frequency (1 core)3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +