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Difference between revisions of "intel/xeon silver/4210"
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|model number=4210 | |model number=4210 | ||
|part number=CD8069503956302 | |part number=CD8069503956302 | ||
+ | |part number 2=BX806954210 | ||
|s-spec=SRFBL | |s-spec=SRFBL | ||
+ | |s-spec qs=QPJF | ||
|market=Server | |market=Server | ||
|first announced=April 2, 2019 | |first announced=April 2, 2019 | ||
Line 26: | Line 28: | ||
|core name=Cascade Lake SP | |core name=Cascade Lake SP | ||
|core family=6 | |core family=6 | ||
− | |core stepping=R1 | + | |core stepping=R0 |
+ | |core stepping 2=R1 | ||
|process=14 nm | |process=14 nm | ||
|technology=CMOS | |technology=CMOS | ||
Line 32: | Line 35: | ||
|core count=10 | |core count=10 | ||
|thread count=20 | |thread count=20 | ||
+ | |max memory=1 TiB | ||
|max cpus=2 | |max cpus=2 | ||
+ | |smp interconnect=UPI | ||
+ | |smp interconnect links=2 | ||
+ | |smp interconnect rate=9.6 GT/s | ||
|tdp=85 W | |tdp=85 W | ||
|tcase min=0 °C | |tcase min=0 °C | ||
|tcase max=78 °C | |tcase max=78 °C | ||
|package name 1=intel,fclga_3647 | |package name 1=intel,fclga_3647 | ||
+ | |predecessor=Xeon Silver 4110 | ||
+ | |predecessor link=intel/xeon silver/4110 | ||
}} | }} | ||
'''Xeon Silver 4210''' is a {{arch|64}} [[deca-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4210 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz. | '''Xeon Silver 4210''' is a {{arch|64}} [[deca-core]] [[x86]] mid-range performance server microprocessor introduced by [[Intel]] in early [[2019]]. The Silver 4210 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is manufactured on a [[14 nm process]]. This chip supports dual-way multiprocessing, sports one {{x86|AVX-512}} [[FMA]] units as well as two {{intel|Ultra Path Interconnect|UPI}} links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a {{intel|turbo boost}} frequency of up to 3.2 GHz. | ||
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|l1d policy=write-back | |l1d policy=write-back | ||
|l2 cache=10 MiB | |l2 cache=10 MiB | ||
− | |l2 break=10x1 | + | |l2 break=10x1 |
|l2 desc=16-way set associative | |l2 desc=16-way set associative | ||
|l2 policy=write-back | |l2 policy=write-back | ||
Line 77: | Line 86: | ||
== Expansions == | == Expansions == | ||
− | {{expansions | + | {{expansions main |
− | | pcie revision | + | | |
− | | pcie lanes | + | {{expansions entry |
− | | pcie config | + | |type=PCIe |
− | | pcie config 2 | + | |pcie revision=3.0 |
− | | pcie config 3 | + | |pcie lanes=48 |
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
}} | }} | ||
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|avx512vbmi=No | |avx512vbmi=No | ||
|avx5124fmaps=No | |avx5124fmaps=No | ||
+ | |avx512vnni=Yes | ||
|avx5124vnniw=No | |avx5124vnniw=No | ||
|avx512vpopcntdq=No | |avx512vpopcntdq=No | ||
Line 131: | Line 145: | ||
|clmul=Yes | |clmul=Yes | ||
|f16c=Yes | |f16c=Yes | ||
+ | |bfloat16=No | ||
|tbt1=No | |tbt1=No | ||
|tbt2=Yes | |tbt2=Yes | ||
Line 140: | Line 155: | ||
|fastmem=No | |fastmem=No | ||
|ivmd=Yes | |ivmd=Yes | ||
+ | |intelnodecontroller=No | ||
|intelnode=Yes | |intelnode=Yes | ||
|kpt=Yes | |kpt=Yes | ||
|ptt=Yes | |ptt=Yes | ||
+ | |intelrunsure=No | ||
|mbe=Yes | |mbe=Yes | ||
|isrt=No | |isrt=No | ||
Line 155: | Line 172: | ||
|vpro=Yes | |vpro=Yes | ||
|vtx=Yes | |vtx=Yes | ||
− | |vtd= | + | |vtd=Yes |
|ept=Yes | |ept=Yes | ||
|mpx=No | |mpx=No | ||
Line 161: | Line 178: | ||
|securekey=No | |securekey=No | ||
|osguard=No | |osguard=No | ||
+ | |intqat=No | ||
+ | |dlboost=Yes | ||
|3dnow=No | |3dnow=No | ||
|e3dnow=No | |e3dnow=No | ||
Line 174: | Line 193: | ||
|sensemi=No | |sensemi=No | ||
|xfr=No | |xfr=No | ||
+ | |xfr2=No | ||
+ | |mxfr=No | ||
+ | |amdpb=No | ||
+ | |amdpb2=No | ||
+ | |amdpbod=No | ||
+ | }} | ||
+ | |||
+ | == Frequencies == | ||
+ | {{see also|intel/frequency_behavior|l1=Intel's CPU Frequency Behavior}} | ||
+ | {{frequency table | ||
+ | |freq_base=2,200MHz | ||
+ | |freq_1=3,200MHz | ||
+ | |freq_2=3,200MHz | ||
+ | |freq_3=3,000MHz | ||
+ | |freq_4=3,000MHz | ||
+ | |freq_5=2,900MHz | ||
+ | |freq_6=2,900MHz | ||
+ | |freq_7=2,900MHz | ||
+ | |freq_8=2,900MHz | ||
+ | |freq_9=2,700MHz | ||
+ | |freq_10=2,700MHz | ||
+ | |freq_avx2_base=1,900MHz | ||
+ | |freq_avx2_1=3,000MHz | ||
+ | |freq_avx2_2=3,000MHz | ||
+ | |freq_avx2_3=2,800MHz | ||
+ | |freq_avx2_4=2,800MHz | ||
+ | |freq_avx2_5=2,500MHz | ||
+ | |freq_avx2_6=2,500MHz | ||
+ | |freq_avx2_7=2,500MHz | ||
+ | |freq_avx2_8=2,500MHz | ||
+ | |freq_avx2_9=2,300MHz | ||
+ | |freq_avx2_10=2,300MHz | ||
+ | |freq_avx512_base=1,200MHz | ||
+ | |freq_avx512_1=2,000MHz | ||
+ | |freq_avx512_2=2,000MHz | ||
+ | |freq_avx512_3=1,800MHz | ||
+ | |freq_avx512_4=1,800MHz | ||
+ | |freq_avx512_5=1,600MHz | ||
+ | |freq_avx512_6=1,600MHz | ||
+ | |freq_avx512_7=1,600MHz | ||
+ | |freq_avx512_8=1,600MHz | ||
+ | |freq_avx512_9=1,500MHz | ||
+ | |freq_avx512_10=1,500MHz | ||
}} | }} |
Latest revision as of 01:33, 24 January 2020
Edit Values | |
Xeon Silver 4210 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 4210 |
Part Number | CD8069503956302, BX806954210 |
S-Spec | SRFBL QPJF (QS) |
Market | Server |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Release Price | $501.00 (tray) $511.00 (box) |
Shop | Amazon |
General Specs | |
Family | Xeon Silver |
Series | 4200 |
Locked | Yes |
Frequency | 2,200 MHz |
Turbo Frequency | 3,200 MHz (1 core) |
Clock multiplier | 22 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Purley |
Chipset | Lewisburg |
Core Name | Cascade Lake SP |
Core Family | 6 |
Core Stepping | R0, R1 |
Process | 14 nm |
Technology | CMOS |
Word Size | 64 bit |
Cores | 10 |
Threads | 20 |
Max Memory | 1 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Interconnect | UPI |
Interconnect Links | 2 |
Interconnect Rate | 9.6 GT/s |
Electrical | |
TDP | 85 W |
Tcase | 0 °C – 78 °C |
Packaging | |
Package | FCLGA-3647 (FCLGA) |
Dimension | 76.16 mm × 56.6 mm |
Pitch | 0.8585 mm × 0.9906 mm |
Contacts | 3647 |
Socket | Socket P, LGA-3647 |
Succession | |
Xeon Silver 4210 is a 64-bit deca-core x86 mid-range performance server microprocessor introduced by Intel in early 2019. The Silver 4210 is based on the Cascade Lake microarchitecture and is manufactured on a 14 nm process. This chip supports dual-way multiprocessing, sports one AVX-512 FMA units as well as two UPI links. This microprocessor supports up 1 TiB of hexa-channel DDR4-2400 memory, operates at 2.2 GHz with a TDP of 85 W and features a turbo boost frequency of up to 3.2 GHz.
Cache[edit]
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Frequencies[edit]
- See also: Intel's CPU Frequency Behavior
Mode | Base | Turbo Frequency/Active Cores | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|
1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | ||
Normal | 2,200MHz | 3,200MHz | 3,200MHz | 3,000MHz | 3,000MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,900MHz | 2,700MHz | 2,700MHz |
AVX2 | 1,900MHz | 3,000MHz | 3,000MHz | 2,800MHz | 2,800MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,500MHz | 2,300MHz | 2,300MHz |
AVX512 | 1,200MHz | 2,000MHz | 2,000MHz | 1,800MHz | 1,800MHz | 1,600MHz | 1,600MHz | 1,600MHz | 1,600MHz | 1,500MHz | 1,500MHz |
Facts about "Xeon Silver 4210 - Intel"
Has subobject "Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki. | Xeon Silver 4210 - Intel#pcie + |
base frequency | 2,200 MHz (2.2 GHz, 2,200,000 kHz) + |
chipset | Lewisburg + |
clock multiplier | 22 + |
core count | 10 + |
core family | 6 + |
core name | Cascade Lake SP + |
core stepping | R0 + and R1 + |
designer | Intel + |
family | Xeon Silver + |
first announced | April 2, 2019 + |
first launched | April 2, 2019 + |
full page name | intel/xeon silver/4210 + |
has advanced vector extensions | true + |
has advanced vector extensions 2 | true + |
has advanced vector extensions 512 | true + |
has ecc memory support | true + |
has extended page tables support | true + |
has feature | Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Vector Extensions 512 +, Advanced Encryption Standard Instruction Set Extension +, Hyper-Threading Technology +, Turbo Boost Technology 2.0 +, Enhanced SpeedStep Technology +, Speed Shift Technology +, Trusted Execution Technology +, Intel vPro Technology +, Intel VT-x +, Intel VT-d +, Extended Page Tables +, Transactional Synchronization Extensions + and Deep Learning Boost + |
has intel deep learning boost | true + |
has intel enhanced speedstep technology | true + |
has intel speed shift technology | true + |
has intel trusted execution technology | true + |
has intel turbo boost technology 2 0 | true + |
has intel vpro technology | true + |
has intel vt-d technology | true + |
has intel vt-x technology | true + |
has locked clock multiplier | true + |
has second level address translation support | true + |
has simultaneous multithreading | true + |
has transactional synchronization extensions | true + |
has x86 advanced encryption standard instruction set extension | true + |
instance of | microprocessor + |
isa | x86-64 + |
isa family | x86 + |
l1$ size | 640 KiB (655,360 B, 0.625 MiB) + |
l1d$ description | 8-way set associative + |
l1d$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l1i$ description | 8-way set associative + |
l1i$ size | 320 KiB (327,680 B, 0.313 MiB) + |
l2$ description | 16-way set associative + |
l2$ size | 10 MiB (10,240 KiB, 10,485,760 B, 0.00977 GiB) + |
l3$ description | 11-way set associative + |
l3$ size | 13.75 MiB (14,080 KiB, 14,417,920 B, 0.0134 GiB) + |
ldate | April 2, 2019 + |
main image | ![]() |
manufacturer | Intel + |
market segment | Server + |
max case temperature | 351.15 K (78 °C, 172.4 °F, 632.07 °R) + |
max cpu count | 2 + |
max memory | 1,048,576 MiB (1,073,741,824 KiB, 1,099,511,627,776 B, 1,024 GiB, 1 TiB) + |
max memory bandwidth | 107.3 GiB/s (109,875.2 MiB/s, 115.212 GB/s, 115,212.498 MB/s, 0.105 TiB/s, 0.115 TB/s) + |
max memory channels | 6 + |
microarchitecture | Cascade Lake + |
min case temperature | 273.15 K (0 °C, 32 °F, 491.67 °R) + |
model number | 4210 + |
name | Xeon Silver 4210 + |
package | FCLGA-3647 + |
part number | CD8069503956302 + and BX806954210 + |
platform | Purley + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |
release price | $ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) + and $ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) + |
release price (box) | $ 511.00 (€ 459.90, £ 413.91, ¥ 52,801.63) + |
release price (tray) | $ 501.00 (€ 450.90, £ 405.81, ¥ 51,768.33) + |
s-spec | SRFBL + |
s-spec (qs) | QPJF + |
series | 4200 + |
smp interconnect | UPI + |
smp interconnect links | 2 + |
smp interconnect rate | 9.6 GT/s + |
smp max ways | 2 + |
socket | Socket P + and LGA-3647 + |
supported memory type | DDR4-2400 + |
tdp | 85 W (85,000 mW, 0.114 hp, 0.085 kW) + |
technology | CMOS + |
thread count | 20 + |
turbo frequency (1 core) | 3,200 MHz (3.2 GHz, 3,200,000 kHz) + |
word size | 64 bit (8 octets, 16 nibbles) + |