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{{intel title|Xeon Platinum 9221}}
 
{{intel title|Xeon Platinum 9221}}
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{{chip}}
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{{chip
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'''Xeon Platinum 9221''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9221 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.1 GHz with a TDP of 250 W and a {{intel|turbo boost}} of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.
+
|name=Xeon Platinum 9221
 +
|image=cascade lake ap (front).png
 +
|designer=Intel
 +
|manufacturer=Intel
 +
|model number=9221
 +
|market=Server
 +
|market 2=HPC
 +
|first announced=April 2, 2019
 +
|first launched=April 2, 2019
 +
|family=Xeon Platinum
 +
|series=9200
 +
|locked=Yes
 +
|frequency=2,100 MHz
 +
|turbo frequency1=3,700 MHz
 +
|bus type=DMI 3.0
 +
|bus links=4
 +
|bus rate=8 GT/s
 +
|clock multiplier=21
 +
|isa=x86-64
 +
|isa family=x86
 +
|microarch=Cascade Lake
 +
|platform=Walker Pass
 +
|chipset=Lewisburg
 +
|core name=Cascade Lake AP
 +
|core family=6
 +
|process=14 nm
 +
|technology=CMOS
 +
|mcp=Yes
 +
|die count=2
 +
|word size=64 bit
 +
|core count=32
 +
|thread count=64
 +
|max cpus=2
 +
|max memory=2 TiB
 +
|tdp=250 W
 +
|package name 1=intel,fcbga_5903
 +
}}
 +
'''Xeon Platinum 9221''' is a [[32-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9221 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.1 GHz with a TDP of 250 W and a {{intel|turbo boost}} of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.
 +
 
 +
This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
 +
 
 +
== Cache ==
 +
{{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Cascade Lake § Cache}}
 +
{{cache size
 +
|l1 cache=2 MiB
 +
|l1i cache=1 MiB
 +
|l1i break=32x32 KiB
 +
|l1i desc=8-way set associative
 +
|l1d cache=1 MiB
 +
|l1d break=32x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=32 MiB
 +
|l2 break=32x1 MiB
 +
|l2 desc=16-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=71.5 MiB
 +
|l3 break=52x1.375 MiB
 +
|l3 desc=11-way set associative
 +
|l3 policy=write-back
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}}
 +
 
 +
== Memory controller ==
 +
{{memory controller
 +
|type=DDR4-2933
 +
|ecc=Yes
 +
|max mem=2 TiB
 +
|controllers=4
 +
|channels=12
 +
|max bandwidth=262.26 GiB/s
 +
|bandwidth schan=21.86 GiB/s
 +
|bandwidth dchan=43.71 GiB/s
 +
|bandwidth qchan=87.42 GiB/s
 +
|bandwidth ochan=174.84 GiB/s
 +
}}
 +
 
 +
== Expansions ==
 +
{{expansions main
 +
|
 +
{{expansions entry
 +
|type=PCIe
 +
|pcie revision=3.0
 +
|pcie lanes=40
 +
|pcie config=1x16
 +
|pcie config 2=x8
 +
|pcie config 3=x4
 +
}}
 +
}}
 +
 
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=No
 +
|avx=Yes
 +
|avx2=Yes
 +
|avx512f=Yes
 +
|avx512cd=Yes
 +
|avx512er=No
 +
|avx512pf=No
 +
|avx512bw=Yes
 +
|avx512dq=Yes
 +
|avx512vl=Yes
 +
|avx512ifma=No
 +
|avx512vbmi=No
 +
|avx5124fmaps=No
 +
|avx512vnni=Yes
 +
|avx5124vnniw=No
 +
|avx512vpopcntdq=No
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=No
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
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|f16c=Yes
 +
|bfloat16=No
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|tbt1=No
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|tbt2=Yes
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|tbmt3=No
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|bpt=No
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|eist=Yes
 +
|sst=Yes
 +
|flex=No
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|fastmem=No
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|ivmd=Yes
 +
|intelnodecontroller=Yes
 +
|intelnode=Yes
 +
|kpt=Yes
 +
|ptt=Yes
 +
|intelrunsure=Yes
 +
|mbe=Yes
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=Yes
 +
|txt=Yes
 +
|ht=Yes
 +
|vpro=Yes
 +
|vtx=Yes
 +
|vtd=Yes
 +
|ept=Yes
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|intqat=No
 +
|dlboost=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=No
 +
|amdv=No
 +
|amdsme=No
 +
|amdtsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=No
 +
|sensemi=No
 +
|xfr=No
 +
|xfr2=No
 +
|mxfr=No
 +
|amdpb=No
 +
|amdpb2=No
 +
|amdpbod=No
 +
}}

Latest revision as of 01:16, 4 June 2019

Edit Values
Xeon Platinum 9221
cascade lake ap (front).png
General Info
DesignerIntel
ManufacturerIntel
Model Number9221
MarketServer, HPC
IntroductionApril 2, 2019 (announced)
April 2, 2019 (launched)
ShopAmazon
General Specs
FamilyXeon Platinum
Series9200
LockedYes
Frequency2,100 MHz
Turbo Frequency3,700 MHz (1 core)
Bus typeDMI 3.0
Bus rate4 × 8 GT/s
Clock multiplier21
Microarchitecture
ISAx86-64 (x86)
MicroarchitectureCascade Lake
PlatformWalker Pass
ChipsetLewisburg
Core NameCascade Lake AP
Core Family6
Process14 nm
TechnologyCMOS
MCPYes (2 dies)
Word Size64 bit
Cores32
Threads64
Max Memory2 TiB
Multiprocessing
Max SMP2-Way (Multiprocessor)
Electrical
TDP250 W
Packaging
PackageFCBGA-5903 (BGA)
Pitch0.99 mm
Contacts5903

Xeon Platinum 9221 is a 32-core 64-bit high-performance x86 server microprocessor introduced by Intel in early 2019. The 9221 is based on the Cascade Lake microarchitecture and is fabricated on Intel's 14 nm process. It operates at 2.1 GHz with a TDP of 250 W and a turbo boost of up to 3.7 GHz. This processor supports up to twelve channels of DDR4-2933 memory.

This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.

Cache[edit]

Main article: Cascade Lake § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$2 MiB
2,048 KiB
2,097,152 B
L1I$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associative 
L1D$1 MiB
1,024 KiB
1,048,576 B
32x32 KiB8-way set associativewrite-back
L2$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  32x1 MiB16-way set associativewrite-back
L3$71.5 MiB
73,216 KiB
74,973,184 B
0.0698 GiB
  52x1.375 MiB11-way set associativewrite-back

Memory controller[edit]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2933
Supports ECCYes
Max Mem2 TiB
Controllers4
Channels12
Max Bandwidth262.26 GiB/s
268,554.24 MiB/s
281.6 GB/s
281,599.531 MB/s
0.256 TiB/s
0.282 TB/s
Bandwidth
Single 21.86 GiB/s
Double 43.71 GiB/s
Quad 87.42 GiB/s
Octa 174.84 GiB/s

Expansions[edit]

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 3.0
Max Lanes: 40
Configuration: 1x16, x8, x4


Features[edit]

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
AVX-512Advanced Vector 512-bit
AVX512FAVX-512 Foundation
AVX512CDAVX-512 Conflict Detection
AVX512BWAVX-512 Byte and Word
AVX512DQAVX-512 Doubleword and Quadword Instructions
AVX512VLAVX-512 Vector Length
AVX512_VNNIAVX-512 Vector Neural Network Instructions
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
HTHyper-Threading
TBT 2.0Turbo Boost Technology 2.0
EISTEnhanced SpeedStep Technology
SSTSpeed Shift Technology
TXTTrusted Execution Technology (SMX)
vProIntel vPro
VT-xVT-x (Virtualization)
VT-dVT-d (I/O MMU virtualization)
EPTExtended Page Tables (SLAT)
TSXTransactional Synchronization Extensions
VMDVolume Management Device
NMNode Manager
KPTKey Protection Technology
PTTPlatform Trust Technology
Run SureRun Sure Technology (RAS Capability)
MBE CtrlMode-Based Execute Control
Node CtrlrNode Controller Support
Retrieved from "https://en.wikichip.org/w/index.php?title=intel/xeon_platinum/9221&oldid=91853"
Facts about "Xeon Platinum 9221 - Intel"
RDF feed
base frequency2,100 MHz (2.1 GHz, 2,100,000 kHz) +
bus links4 +
bus rate8,000 MT/s (8 GT/s, 8,000,000 kT/s) +
bus typeDMI 3.0 +
chipsetLewisburg +
clock multiplier21 +
core count32 +
core family6 +
core nameCascade Lake AP +
designerIntel +
die count2 +
familyXeon Platinum +
first announcedApril 2, 2019 +
first launchedApril 2, 2019 +
full page nameintel/xeon platinum/9221 +
has locked clock multipliertrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
ldateApril 2, 2019 +
main imageFile:cascade lake ap (front).png +
manufacturerIntel +
market segmentServer + and HPC +
max cpu count2 +
max memory2,097,152 MiB (2,147,483,648 KiB, 2,199,023,255,552 B, 2,048 GiB, 2 TiB) +
microarchitectureCascade Lake +
model number9221 +
nameXeon Platinum 9221 +
packageFCBGA-5903 +
platformWalker Pass +
process14 nm (0.014 μm, 1.4e-5 mm) +
series9200 +
smp max ways2 +
tdp250 W (250,000 mW, 0.335 hp, 0.25 kW) +
technologyCMOS +
thread count64 +
turbo frequency (1 core)3,700 MHz (3.7 GHz, 3,700,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +