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Difference between revisions of "intel/xeon platinum/9282"
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{{intel title|Xeon Platinum 9282}} | {{intel title|Xeon Platinum 9282}} | ||
− | {{chip}} | + | {{chip |
+ | |name=Xeon Platinum 9282 | ||
+ | |image=cascade lake ap (front).png | ||
+ | |designer=Intel | ||
+ | |manufacturer=Intel | ||
+ | |model number=9282 | ||
+ | |market=Server | ||
+ | |market 2=HPC | ||
+ | |first announced=April 2, 2019 | ||
+ | |first launched=April 2, 2019 | ||
+ | |family=Xeon Platinum | ||
+ | |series=9200 | ||
+ | |locked=Yes | ||
+ | |frequency=2,600 MHz | ||
+ | |turbo frequency1=3,800 MHz | ||
+ | |bus type=DMI 3.0 | ||
+ | |bus links=4 | ||
+ | |bus rate=8 GT/s | ||
+ | |clock multiplier=26 | ||
+ | |isa=x86-64 | ||
+ | |isa family=x86 | ||
+ | |microarch=Cascade Lake | ||
+ | |platform=Walker Pass | ||
+ | |chipset=Lewisburg | ||
+ | |core name=Cascade Lake AP | ||
+ | |core family=6 | ||
+ | |process=14 nm | ||
+ | |technology=CMOS | ||
+ | |mcp=Yes | ||
+ | |die count=2 | ||
+ | |word size=64 bit | ||
+ | |core count=56 | ||
+ | |thread count=112 | ||
+ | |max memory=2 TiB | ||
+ | |max cpus=2 | ||
+ | |tdp=400 W | ||
+ | |package name 1=intel,fcbga_5903 | ||
+ | }} | ||
+ | '''Xeon Platinum 9282''' is a [[56-core]] {{arch|64}} high-performance [[x86]] server microprocessor introduced by Intel in early [[2019]]. The 9282 is based on the {{intel|Cascade Lake|l=arch}} microarchitecture and is fabricated on Intel's [[14 nm process]]. It operates at 2.6 GHz with a TDP of 400 W and a {{intel|turbo boost}} of up to 3.8 GHz. This processor supports up to twelve channels of DDR4-2933 memory. | ||
+ | |||
+ | This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module. | ||
+ | |||
+ | == Cache == | ||
+ | {{main|intel/microarchitectures/cascade_lake#Memory_Hierarchy|l1=Cascade Lake § Cache}} | ||
+ | {{cache size | ||
+ | |l1 cache=3.5 MiB | ||
+ | |l1i cache=1.75 MiB | ||
+ | |l1i break=56x32 KiB | ||
+ | |l1i desc=8-way set associative | ||
+ | |l1d cache=1.75 MiB | ||
+ | |l1d break=56x32 KiB | ||
+ | |l1d desc=8-way set associative | ||
+ | |l1d policy=write-back | ||
+ | |l2 cache=56 MiB | ||
+ | |l2 break=56x1 MiB | ||
+ | |l2 desc=16-way set associative | ||
+ | |l2 policy=write-back | ||
+ | |l3 cache=77 MiB | ||
+ | |l3 break=56x1.375 MiB | ||
+ | |l3 desc=11-way set associative | ||
+ | |l3 policy=write-back | ||
+ | }} | ||
+ | |||
+ | == Memory controller == | ||
+ | {{memory controller | ||
+ | |type=DDR4-2933 | ||
+ | |ecc=Yes | ||
+ | |max mem=2 TiB | ||
+ | |controllers=4 | ||
+ | |channels=12 | ||
+ | |max bandwidth=262.26 GiB/s | ||
+ | |bandwidth schan=21.86 GiB/s | ||
+ | |bandwidth dchan=43.71 GiB/s | ||
+ | |bandwidth qchan=87.42 GiB/s | ||
+ | |bandwidth ochan=174.84 GiB/s | ||
+ | }} | ||
+ | |||
+ | == Expansions == | ||
+ | {{expansions main | ||
+ | | | ||
+ | {{expansions entry | ||
+ | |type=PCIe | ||
+ | |pcie revision=3.0 | ||
+ | |pcie lanes=40 | ||
+ | |pcie config=1x16 | ||
+ | |pcie config 2=x8 | ||
+ | |pcie config 3=x4 | ||
+ | }} | ||
+ | }} | ||
+ | |||
+ | == Features == | ||
+ | {{x86 features | ||
+ | |real=Yes | ||
+ | |protected=Yes | ||
+ | |smm=Yes | ||
+ | |fpu=Yes | ||
+ | |x8616=Yes | ||
+ | |x8632=Yes | ||
+ | |x8664=Yes | ||
+ | |nx=Yes | ||
+ | |mmx=Yes | ||
+ | |emmx=Yes | ||
+ | |sse=Yes | ||
+ | |sse2=Yes | ||
+ | |sse3=Yes | ||
+ | |ssse3=Yes | ||
+ | |sse41=Yes | ||
+ | |sse42=Yes | ||
+ | |sse4a=Yes | ||
+ | |sse_gfni=Yes | ||
+ | |avx=Yes | ||
+ | |avx_gfni=Yes | ||
+ | |avx2=Yes | ||
+ | |avx512f=Yes | ||
+ | |avx512cd=Yes | ||
+ | |avx512er=Yes | ||
+ | |avx512pf=Yes | ||
+ | |avx512bw=Yes | ||
+ | |avx512dq=Yes | ||
+ | |avx512vl=Yes | ||
+ | |avx512ifma=Yes | ||
+ | |avx512vbmi=Yes | ||
+ | |avx5124fmaps=Yes | ||
+ | |avx512vnni=Yes | ||
+ | |avx5124vnniw=Yes | ||
+ | |avx512vpopcntdq=Yes | ||
+ | |avx512gfni=Yes | ||
+ | |avx512vaes=Yes | ||
+ | |avx512vbmi2=Yes | ||
+ | |avx512bitalg=Yes | ||
+ | |avx512vpclmulqdq=Yes | ||
+ | |abm=Yes | ||
+ | |tbm=Yes | ||
+ | |bmi1=Yes | ||
+ | |bmi2=Yes | ||
+ | |fma3=Yes | ||
+ | |fma4=Yes | ||
+ | |aes=Yes | ||
+ | |rdrand=Yes | ||
+ | |sha=Yes | ||
+ | |xop=Yes | ||
+ | |adx=Yes | ||
+ | |clmul=Yes | ||
+ | |f16c=Yes | ||
+ | |bfloat16=Yes | ||
+ | |tbt1=Yes | ||
+ | |tbt2=Yes | ||
+ | |tbmt3=Yes | ||
+ | |tvb=Yes | ||
+ | |bpt=Yes | ||
+ | |eist=Yes | ||
+ | |sst=Yes | ||
+ | |flex=Yes | ||
+ | |fastmem=Yes | ||
+ | |ivmd=Yes | ||
+ | |intelnodecontroller=Yes | ||
+ | |intelnode=Yes | ||
+ | |kpt=Yes | ||
+ | |ptt=Yes | ||
+ | |intelrunsure=Yes | ||
+ | |mbe=Yes | ||
+ | |isrt=Yes | ||
+ | |sba=Yes | ||
+ | |mwt=Yes | ||
+ | |sipp=Yes | ||
+ | |att=Yes | ||
+ | |ipt=Yes | ||
+ | |tsx=Yes | ||
+ | |txt=Yes | ||
+ | |ht=Yes | ||
+ | |vpro=Yes | ||
+ | |vtx=Yes | ||
+ | |vtd=Yes | ||
+ | |ept=Yes | ||
+ | |mpx=Yes | ||
+ | |sgx=Yes | ||
+ | |securekey=Yes | ||
+ | |osguard=Yes | ||
+ | |intqat=Yes | ||
+ | |dlboost=Yes | ||
+ | |3dnow=Yes | ||
+ | |e3dnow=Yes | ||
+ | |smartmp=Yes | ||
+ | |powernow=Yes | ||
+ | |amdvi=Yes | ||
+ | |amdv=Yes | ||
+ | |amdsme=Yes | ||
+ | |amdtsme=Yes | ||
+ | |amdsev=Yes | ||
+ | |rvi=Yes | ||
+ | |smt=Yes | ||
+ | |sensemi=Yes | ||
+ | |xfr=Yes | ||
+ | |xfr2=Yes | ||
+ | |mxfr=Yes | ||
+ | |amdpb=Yes | ||
+ | |amdpb2=Yes | ||
+ | |amdpbod=Yes | ||
+ | }} |
Latest revision as of 04:34, 31 July 2022
Edit Values | |
Xeon Platinum 9282 | |
![]() | |
General Info | |
Designer | Intel |
Manufacturer | Intel |
Model Number | 9282 |
Market | Server, HPC |
Introduction | April 2, 2019 (announced) April 2, 2019 (launched) |
Shop | Amazon |
General Specs | |
Family | Xeon Platinum |
Series | 9200 |
Locked | Yes |
Frequency | 2,600 MHz |
Turbo Frequency | 3,800 MHz (1 core) |
Bus type | DMI 3.0 |
Bus rate | 4 × 8 GT/s |
Clock multiplier | 26 |
Microarchitecture | |
ISA | x86-64 (x86) |
Microarchitecture | Cascade Lake |
Platform | Walker Pass |
Chipset | Lewisburg |
Core Name | Cascade Lake AP |
Core Family | 6 |
Process | 14 nm |
Technology | CMOS |
MCP | Yes (2 dies) |
Word Size | 64 bit |
Cores | 56 |
Threads | 112 |
Max Memory | 2 TiB |
Multiprocessing | |
Max SMP | 2-Way (Multiprocessor) |
Electrical | |
TDP | 400 W |
Packaging | |
Package | FCBGA-5903 (BGA) |
Pitch | 0.99 mm |
Contacts | 5903 |
Xeon Platinum 9282 is a 56-core 64-bit high-performance x86 server microprocessor introduced by Intel in early 2019. The 9282 is based on the Cascade Lake microarchitecture and is fabricated on Intel's 14 nm process. It operates at 2.6 GHz with a TDP of 400 W and a turbo boost of up to 3.8 GHz. This processor supports up to twelve channels of DDR4-2933 memory.
This processor cannot be purchased independently and is only sold as part of Intel's S9200WK Compute Module.
Contents
Cache[edit]
- Main article: Cascade Lake § Cache
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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Memory controller[edit]
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Integrated Memory Controller
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Expansions[edit]
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Expansion Options |
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Features[edit]
[Edit/Modify Supported Features]
Facts about "Xeon Platinum 9282 - Intel"
full page name | intel/xeon platinum/9282 + |
instance of | microprocessor + |
ldate | 1900 + |